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author | Richard Sandiford <richard.sandiford@linaro.org> | 2011-05-03 07:46:54 +0000 |
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committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2011-05-03 07:46:54 +0000 |
commit | 272c6793a0d2098195c7996bd29c0c7e066486bc (patch) | |
tree | c68ece441c93f241be213a12f649634ce972f325 /gcc/doc | |
parent | 0f6d54f720796f2ebcb15764ac0d0b174529367d (diff) | |
download | gcc-272c6793a0d2098195c7996bd29c0c7e066486bc.zip gcc-272c6793a0d2098195c7996bd29c0c7e066486bc.tar.gz gcc-272c6793a0d2098195c7996bd29c0c7e066486bc.tar.bz2 |
md.texi (vec_load_lanes, [...]): Document.
gcc/
* doc/md.texi (vec_load_lanes, vec_store_lanes): Document.
* optabs.h (COI_vec_load_lanes, COI_vec_store_lanes): New
convert_optab_index values.
(vec_load_lanes_optab, vec_store_lanes_optab): New convert optabs.
* genopinit.c (optabs): Initialize the new optabs.
* internal-fn.def (LOAD_LANES, STORE_LANES): New internal functions.
* internal-fn.c (get_multi_vector_move, expand_LOAD_LANES)
(expand_STORE_LANES): New functions.
* tree.h (build_array_type_nelts): Declare.
* tree.c (build_array_type_nelts): New function.
* tree-vectorizer.h (vect_model_store_cost): Add a bool argument.
(vect_model_load_cost): Likewise.
(vect_store_lanes_supported, vect_load_lanes_supported)
(vect_record_strided_load_vectors): Declare.
* tree-vect-data-refs.c (vect_lanes_optab_supported_p)
(vect_store_lanes_supported, vect_load_lanes_supported): New functions.
(vect_transform_strided_load): Split out statement recording into...
(vect_record_strided_load_vectors): ...this new function.
* tree-vect-stmts.c (create_vector_array, read_vector_array)
(write_vector_array, create_array_ref): New functions.
(vect_model_store_cost): Add store_lanes_p argument.
(vect_model_load_cost): Add load_lanes_p argument.
(vectorizable_store): Try to use store-lanes functions for
interleaved stores.
(vectorizable_load): Likewise load-lanes and loads.
* tree-vect-slp.c (vect_get_and_check_slp_defs): Update call
to vect_model_store_cost.
(vect_build_slp_tree): Likewise vect_model_load_cost.
From-SVN: r173291
Diffstat (limited to 'gcc/doc')
-rw-r--r-- | gcc/doc/md.texi | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index df99ad4..0e68db7 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3846,6 +3846,48 @@ into consecutive memory locations. Operand 0 is the first of the consecutive memory locations, operand 1 is the first register, and operand 2 is a constant: the number of consecutive registers. +@cindex @code{vec_load_lanes@var{m}@var{n}} instruction pattern +@item @samp{vec_load_lanes@var{m}@var{n}} +Perform an interleaved load of several vectors from memory operand 1 +into register operand 0. Both operands have mode @var{m}. The register +operand is viewed as holding consecutive vectors of mode @var{n}, +while the memory operand is a flat array that contains the same number +of elements. The operation is equivalent to: + +@smallexample +int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n}); +for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++) + for (i = 0; i < c; i++) + operand0[i][j] = operand1[j * c + i]; +@end smallexample + +For example, @samp{vec_load_lanestiv4hi} loads 8 16-bit values +from memory into a register of mode @samp{TI}@. The register +contains two consecutive vectors of mode @samp{V4HI}@. + +This pattern can only be used if: +@smallexample +TARGET_ARRAY_MODE_SUPPORTED_P (@var{n}, @var{c}) +@end smallexample +is true. GCC assumes that, if a target supports this kind of +instruction for some mode @var{n}, it also supports unaligned +loads for vectors of mode @var{n}. + +@cindex @code{vec_store_lanes@var{m}@var{n}} instruction pattern +@item @samp{vec_store_lanes@var{m}@var{n}} +Equivalent to @samp{vec_load_lanes@var{m}@var{n}}, with the memory +and register operands reversed. That is, the instruction is +equivalent to: + +@smallexample +int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n}); +for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++) + for (i = 0; i < c; i++) + operand0[j * c + i] = operand1[i][j]; +@end smallexample + +for a memory operand 0 and register operand 1. + @cindex @code{vec_set@var{m}} instruction pattern @item @samp{vec_set@var{m}} Set given field in the vector value. Operand 0 is the vector to modify, |