RISC-V: Implement C[LT]Z_DEFINED_VALUE_AT_ZERO

The Zbb support has introduced ctz and clz to the backend, but some
transformations in GCC need to know what the value of c[lt]z at zero
is. This affects how the optab is generated and may suppress use of
CLZ/CTZ in tree passes.

Among other things, this is needed for the transformation of
table-based ctz-implementations, such as in deepsjeng, to work
(see https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90838).

Prior to this change, the test case from PR90838 would compile to
on RISC-V targets with Zbb:
  myctz:
	lui	a4,%hi(.LC0)
	ld	a4,%lo(.LC0)(a4)
	neg	a5,a0
	and	a5,a5,a0
	mul	a5,a5,a4
	lui	a4,%hi(.LANCHOR0)
	addi	a4,a4,%lo(.LANCHOR0)
	srli	a5,a5,58
	sh2add	a5,a5,a4
	lw	a0,0(a5)
	ret

After this change, we get:
  myctz:
	ctz	a0,a0
	andi	a0,a0,63
	ret

Testing this with deepsjeng_r (from SPEC 2017) against QEMU, this
shows a clear reduction in dynamic instruction count:
 - before  1961888067076
 - after   1907928279874 (2.75% reduction)

This also merges the various target-specific test-cases (for x86-64,
aarch64 and riscv) within gcc.dg/pr90838.c.

This extends the macros (i.e., effective-target keywords) used in
testing (lib/target-supports.exp) to reliably distinguish between RV32
and RV64 via __riscv_xlen (i.e., the integer register bitwidth) :
testing for ILP32 could be misleading (as ILP32 is a valid memory
model for 64bit systems).

gcc/ChangeLog:

	* config/riscv/riscv.h (CLZ_DEFINED_VALUE_AT_ZERO): Implement.
	(CTZ_DEFINED_VALUE_AT_ZERO): Same.
	* doc/sourcebuild.texi: add documentation for RISC-V specific
	test target keywords

gcc/testsuite/ChangeLog:

	* gcc.dg/pr90838.c: Add additional flags (dg-additional-options)
	  when compiling for riscv64 and subsume gcc.target/aarch64/pr90838.c
	  and gcc.target/i386/pr95863-2.c.
	* gcc.target/aarch64/pr90838.c: Removed.
	* gcc.target/i386/pr95863-2.c: Removed.
	* lib/target-supports.exp: Recognize RV32 or RV64 via XLEN

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Signed-off-by: Manolis Tsamis <manolis.tsamis@vrull.eu>
Co-authored-by: Manolis Tsamis <manolis.tsamis@vrull.eu>

1 files changed, 12 insertions, 0 deletions

diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 613ac29..71c0484 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2420,6 +2420,18 @@ PowerPC target pre-defines macro _ARCH_PWR9 which means the @code{-mcpu}
 setting is Power9 or later.
 @end table
 
+@subsection RISC-V specific attributes
+
+@table @code
+
+@item rv32
+Test system has an integer register width of 32 bits.
+
+@item rv64
+Test system has an integer register width of 64 bits.
+
+@end table
+
 @subsubsection Other hardware attributes
 
 @c Please keep this table sorted alphabetically.