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| author | Joseph Myers <joseph@codesourcery.com> | 2005-11-22 00:35:48 +0000 |
|---|---|---|
| committer | Joseph Myers <jsm28@gcc.gnu.org> | 2005-11-22 00:35:48 +0000 |
| commit | 131aeb82d18736392c992c79c2184b2ad16c6190 (patch) | |
| tree | 7ab67e5bc186d42f2dd5968d92d477a5936aeb7f /gcc/doc | |
| parent | b967bf2560748664c1afbdb7d4576a522b00175d (diff) | |
| download | gcc-131aeb82d18736392c992c79c2184b2ad16c6190.zip gcc-131aeb82d18736392c992c79c2184b2ad16c6190.tar.gz gcc-131aeb82d18736392c992c79c2184b2ad16c6190.tar.bz2 | |
rs6000.opt (mmulhw): New option.
* config/rs6000/rs6000.opt (mmulhw): New option.
* doc/invoke.texi (-mmulhw): Document.
* config/rs6000/rs6000.c (rs6000_override_options): Enable -mmulhw
for 405 and 440.
* config/rs6000/rs6000.md: Add half-word multiply and
multiply-accumulate instructions for 405 and 440.
testsuite:
* gcc.target/powerpc/405-macchw-1.c,
gcc.target/powerpc/405-macchw-2.c,
gcc.target/powerpc/405-macchwu-1.c,
gcc.target/powerpc/405-macchwu-2.c,
gcc.target/powerpc/405-machhw-1.c,
gcc.target/powerpc/405-machhw-2.c,
gcc.target/powerpc/405-machhwu-1.c,
gcc.target/powerpc/405-machhwu-2.c,
gcc.target/powerpc/405-maclhw-1.c,
gcc.target/powerpc/405-maclhw-2.c,
gcc.target/powerpc/405-maclhwu-1.c,
gcc.target/powerpc/405-maclhwu-2.c,
gcc.target/powerpc/405-mulchw-1.c,
gcc.target/powerpc/405-mulchw-2.c,
gcc.target/powerpc/405-mulchwu-1.c,
gcc.target/powerpc/405-mulchwu-2.c,
gcc.target/powerpc/405-mulhhw-1.c,
gcc.target/powerpc/405-mulhhw-2.c,
gcc.target/powerpc/405-mulhhwu-1.c,
gcc.target/powerpc/405-mulhhwu-2.c,
gcc.target/powerpc/405-mullhw-1.c,
gcc.target/powerpc/405-mullhw-2.c,
gcc.target/powerpc/405-mullhwu-1.c,
gcc.target/powerpc/405-mullhwu-2.c,
gcc.target/powerpc/405-nmacchw-1.c,
gcc.target/powerpc/405-nmacchw-2.c,
gcc.target/powerpc/405-nmachhw-1.c,
gcc.target/powerpc/405-nmachhw-2.c,
gcc.target/powerpc/405-nmaclhw-1.c,
gcc.target/powerpc/405-nmaclhw-2.c,
gcc.target/powerpc/440-macchw-1.c,
gcc.target/powerpc/440-macchw-2.c,
gcc.target/powerpc/440-macchwu-1.c,
gcc.target/powerpc/440-macchwu-2.c,
gcc.target/powerpc/440-machhw-1.c,
gcc.target/powerpc/440-machhw-2.c,
gcc.target/powerpc/440-machhwu-1.c,
gcc.target/powerpc/440-machhwu-2.c,
gcc.target/powerpc/440-maclhw-1.c,
gcc.target/powerpc/440-maclhw-2.c,
gcc.target/powerpc/440-maclhwu-1.c,
gcc.target/powerpc/440-maclhwu-2.c,
gcc.target/powerpc/440-mulchw-1.c,
gcc.target/powerpc/440-mulchw-2.c,
gcc.target/powerpc/440-mulchwu-1.c,
gcc.target/powerpc/440-mulchwu-2.c,
gcc.target/powerpc/440-mulhhw-1.c,
gcc.target/powerpc/440-mulhhw-2.c,
gcc.target/powerpc/440-mulhhwu-1.c,
gcc.target/powerpc/440-mulhhwu-2.c,
gcc.target/powerpc/440-mullhw-1.c,
gcc.target/powerpc/440-mullhw-2.c,
gcc.target/powerpc/440-mullhwu-1.c,
gcc.target/powerpc/440-mullhwu-2.c,
gcc.target/powerpc/440-nmacchw-1.c,
gcc.target/powerpc/440-nmacchw-2.c,
gcc.target/powerpc/440-nmachhw-1.c,
gcc.target/powerpc/440-nmachhw-2.c,
gcc.target/powerpc/440-nmaclhw-1.c,
gcc.target/powerpc/440-nmaclhw-2.c: New tests.
From-SVN: r107344
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/invoke.texi | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 1f430bb..c8a72c4 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -659,6 +659,7 @@ See RS/6000 and PowerPC Options. -mspe -mno-spe @gol -mspe=yes -mspe=no @gol -mvrsave -mno-vrsave @gol +-mmulhw -mno-mulhw @gol -mfloat-gprs=yes -mfloat-gprs=no -mfloat-gprs=single -mfloat-gprs=double @gol -mprototype -mno-prototype @gol -msim -mmvme -mads -myellowknife -memb -msdata @gol @@ -10974,7 +10975,8 @@ following options: @option{-maltivec}, @option{-mfprnd}, @option{-mhard-float}, @option{-mmfcrf}, @option{-mmultiple}, @option{-mnew-mnemonics}, @option{-mpopcntb}, @option{-mpower}, @option{-mpower2}, @option{-mpowerpc64}, @option{-mpowerpc-gpopt}, -@option{-mpowerpc-gfxopt}, @option{-mstring}. The particular options +@option{-mpowerpc-gfxopt}, @option{-mstring}, @option{-mmulhw}. +The particular options set for any particular CPU will vary between compiler versions, depending on what setting seems to produce optimal code for that CPU; it doesn't necessarily reflect the actual hardware's capabilities. If @@ -11236,6 +11238,15 @@ Generate code that uses (does not use) the floating point multiply and accumulate instructions. These instructions are generated by default if hardware floating is used. +@item -mmulhw +@itemx -mno-mulhw +@opindex mmulhw +@opindex mno-mulhw +Generate code that uses (does not use) the half-word multiply and +multiply-accumulate instructions on the IBM 405 and 440 processors. +These instructions are generated by default when targetting those +processors. + @item -mno-bit-align @itemx -mbit-align @opindex mno-bit-align |