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authorAndreas Krebbel <krebbel@linux.ibm.com>2021-07-29 08:03:36 +0200
committerAndreas Krebbel <krebbel@linux.ibm.com>2021-07-29 08:03:36 +0200
commit841548f0f7d375c5b7022e19d588061cda3acfa6 (patch)
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parente8de5bad250909c9599da49d07f09fb9a8cabd0f (diff)
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Adjust docu of TARGET_VECTORIZE_VEC_PERM_CONST
gcc/ChangeLog: * target.def: in0 and in1 do not need to be registers. * doc/tm.texi: Regenerate.
Diffstat (limited to 'gcc/doc/tm.texi')
-rw-r--r--gcc/doc/tm.texi2
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index d5f8852..a464d26 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -6125,7 +6125,7 @@ vectors of mode @var{mode} using the permutation vector @code{sel}, and
also to emit such a permutation. In the former case @var{in0}, @var{in1}
and @var{out} are all null. In the latter case @var{in0} and @var{in1} are
the source vectors and @var{out} is the destination vector; all three are
-registers of mode @var{mode}. @var{in1} is the same as @var{in0} if
+operands of mode @var{mode}. @var{in1} is the same as @var{in0} if
@var{sel} describes a permutation on one vector instead of two.
Return true if the operation is possible, emitting instructions for it