2007-xx-xx Chao-ying Fu <fu@mips.com> Richard Sandiford <richard@nildram.co.uk>

gcc/
2007-xx-xx  Chao-ying Fu  <fu@mips.com>
	    Richard Sandiford  <richard@nildram.co.uk>

	* doc/md.texi (madd@var{m}@var{n}4, umadd@var{m}@var{n}4): Document.
	* optabs.h (OTI_smadd_widen, OTI_umadd_widen): New optab_indexes.
	(smadd_widen_optab, umadd_widen_optab): Define.
	* optabs.c (init_optabs): Initialize smadd_widen_optab and
	umadd_widen_optab.
	* genopinit.c (optabs): Fill in smadd_widen_optab and
	umadd_widen_optab.
	* expr.c (expand_expr_real_1): Try to use smadd_widen_optab
	and umadd_widen_optab to implement multiply-add sequences.
	* config/mips/mips.md (*<su>mul_acc_di): Rename to...
	(<u>maddsidi4): ...this.  Extend condition to include
	GENERATE_MADD_MSUB and TARGET_DSPR2.  Change the constraint
	of operand 0 to "ka" and use the three-operand form of madd<u>
	for TARGET_DSPR2.
	* config/mips/mips-dspr2.md (mips_madd, mips_maddu): Convert
	to define_expands.
	* config/mips/constraints.md (ka): New register constraint.

gcc/testsuite/
2007-xx-xx  Richard Sandiford  <richard@nildram.co.uk>

	* gcc.target/mips/madd-1.c, gcc.target/mips/madd-2.c,
	* gcc.target/mips/madd-3.c, gcc.target/mips/madd-4.c,
	* gcc.target/mips/maddu-1.c, gcc.target/mips/maddu-2.c,
	* gcc.target/mips/maddu-3.c, gcc.target/mips/maddu-4.c: New tests.

From-SVN: r124095

1 files changed, 18 insertions, 0 deletions

diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 01705ad..56cc60f 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3669,6 +3669,24 @@ The least significant half of the product is discarded.
 @item @samp{umul@var{m}3_highpart}
 Similar, but the multiplication is unsigned.
 
+@cindex @code{madd@var{m}@var{n}4} instruction pattern
+@item @samp{madd@var{m}@var{n}4}
+Multiply operands 1 and 2, sign-extend them to mode @var{n}, add
+operand 3, and store the result in operand 0.  Operands 1 and 2
+have mode @var{m} and operands 0 and 3 have mode @var{n}.
+Both modes must be integer modes and @var{n} must be twice
+the size of @var{m}.
+
+In other words, @code{madd@var{m}@var{n}4} is like
+@code{mul@var{m}@var{n}3} except that it also adds operand 3.
+
+These instructions are not allowed to @code{FAIL}.
+
+@cindex @code{umadd@var{m}@var{n}4} instruction pattern
+@item @samp{umadd@var{m}@var{n}4}
+Like @code{madd@var{m}@var{n}4}, but zero-extend the multiplication
+operands instead of sign-extending them.
+
 @cindex @code{divmod@var{m}4} instruction pattern
 @item @samp{divmod@var{m}4}
 Signed division that produces both a quotient and a remainder.