rs6000.h (enum r6000_reg_class_enum): Add new constraints: wu, ww, and wy.

2013-09-20  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add new
	constraints: wu, ww, and wy.  Repurpose wv constraint added during
	power8 changes.  Put wg constraint in alphabetical order.

	* config/rs6000/rs6000.opt (-mvsx-scalar-float): New debug switch
	for future work to add ISA 2.07 VSX single precision support.
	(-mvsx-scalar-double): Change default from -1 to 1, update
	documentation comment.
	(-mvsx-scalar-memory): Rename debug switch to -mupper-regs-df.
	(-mupper-regs-df): New debug switch to control whether DF values
	can go in the traditional Altivec registers.
	(-mupper-regs-sf): New debug switch to control whether SF values
	can go in the traditional Altivec registers.

	* config/rs6000/rs6000.c (rs6000_debug_reg_global): Print wu, ww,
	and wy constraints.
	(rs6000_init_hard_regno_mode_ok): Use ssize_t instead of int for
	loop variables.  Rename -mvsx-scalar-memory to -mupper-regs-df.
	Add new constraints, wu/ww/wy.  Repurpose wv constraint.
	(rs6000_debug_legitimate_address_p): Print if we are running
	before, during, or after reload.
	(rs6000_secondary_reload): Add a comment.
	(rs6000_opt_masks): Add -mupper-regs-df, -mupper-regs-sf.

	* config/rs6000/constraints.md (wa constraint): Sort w<x>
	constraints.  Update documentation string.
	(wd constraint): Likewise.
	(wf constraint): Likewise.
	(wg constraint): Likewise.
	(wn constraint): Likewise.
	(ws constraint): Likewise.
	(wt constraint): Likewise.
	(wx constraint): Likewise.
	(wz constraint): Likewise.
	(wu constraint): New constraint for ISA 2.07 SFmode scalar
	instructions.
	(ww constraint): Likewise.
	(wy constraint): Likewise.
	(wv constraint): Repurpose ISA 2.07 constraint that we not used in
	the previous submissions.
	* doc/md.texi (PowerPC and IBM RS6000): Likewise.

From-SVN: r202843

1 files changed, 24 insertions, 12 deletions

diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 5776046..45ea45a 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -2067,40 +2067,52 @@ Floating point register (containing 32-bit value)
 Altivec vector register
 
 @item wa
-Any VSX register
+Any VSX register if the -mvsx option was used or NO_REGS.
 
 @item wd
-VSX vector register to hold vector double data
+VSX vector register to hold vector double data or NO_REGS.
 
 @item wf
-VSX vector register to hold vector float data
+VSX vector register to hold vector float data or NO_REGS.
 
 @item wg
-If @option{-mmfpgpr} was used, a floating point register
+If @option{-mmfpgpr} was used, a floating point register or NO_REGS.
 
 @item wl
-If the LFIWAX instruction is enabled, a floating point register
+Floating point register if the LFIWAX instruction is enabled or NO_REGS.
 
 @item wm
-If direct moves are enabled, a VSX register.
+VSX register if direct move instructions are enabled, or NO_REGS.
 
 @item wn
-No register.
+No register (NO_REGS).
 
 @item wr
-General purpose register if 64-bit mode is used
+General purpose register if 64-bit instructions are enabled or NO_REGS.
 
 @item ws
-VSX vector register to hold scalar float data
+VSX vector register to hold scalar double values or NO_REGS.
 
 @item wt
-VSX vector register to hold 128 bit integer
+VSX vector register to hold 128 bit integer or NO_REGS.
+
+@item wu
+Altivec register to use for float/32-bit int loads/stores  or NO_REGS.
+
+@item wv
+Altivec register to use for double loads/stores  or NO_REGS.
+
+@item ww
+FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS.
 
 @item wx
-If the STFIWX instruction is enabled, a floating point register
+Floating point register if the STFIWX instruction is enabled or NO_REGS.
+
+@item wy
+VSX vector register to hold scalar float values or NO_REGS.
 
 @item wz
-If the LFIWZX instruction is enabled, a floating point register
+Floating point register if the LFIWZX instruction is enabled or NO_REGS.
 
 @item wQ
 A memory address that will work with the @code{lq} and @code{stq}