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author | Ian Bolton <ian.bolton@arm.com> | 2012-10-23 17:06:03 +0000 |
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committer | Marcus Shawcroft <mshawcroft@gcc.gnu.org> | 2012-10-23 17:06:03 +0000 |
commit | 5c0da01859030ded4150e4bf9f1c93c7d800c863 (patch) | |
tree | db9613237afdf7e4dba46ea5562b4ac61f6c26c1 /gcc/doc/md.texi | |
parent | 43e9d192f17550753d62debb7f1d8bc9ecab2360 (diff) | |
download | gcc-5c0da01859030ded4150e4bf9f1c93c7d800c863.zip gcc-5c0da01859030ded4150e4bf9f1c93c7d800c863.tar.gz gcc-5c0da01859030ded4150e4bf9f1c93c7d800c863.tar.bz2 |
AArch64 [2/10]
2012-10-23 Ian Bolton <ian.bolton@arm.com>
James Greenhalgh <james.greenhalgh@arm.com>
Jim MacArthur <jim.macarthur@arm.com>
Chris Schlumberger-Socha <chris.schlumberger-socha@arm.com>
Marcus Shawcroft <marcus.shawcroft@arm.com>
Nigel Stephens <nigel.stephens@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Richard Earnshaw <rearnsha@arm.com>
Sofiane Naci <sofiane.naci@arm.com>
Stephen Thomas <stephen,thomas@arm.com>
Tejas Belagod <tejas.belagod@arm.com>
Yufeng Zhang <yufeng.zhang@arm.com>
* doc/invoke.texi (AArch64 Options): New.
* doc/md.texi (Machine Constraints): Add AArch64.
Co-Authored-By: Chris Schlumberger-Socha <chris.schlumberger-socha@arm.com>
Co-Authored-By: James Greenhalgh <james.greenhalgh@arm.com>
Co-Authored-By: Jim MacArthur <jim.macarthur@arm.com>
Co-Authored-By: Marcus Shawcroft <marcus.shawcroft@arm.com>
Co-Authored-By: Nigel Stephens <nigel.stephens@arm.com>
Co-Authored-By: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Co-Authored-By: Richard Earnshaw <rearnsha@arm.com>
Co-Authored-By: Sofiane Naci <sofiane.naci@arm.com>
Co-Authored-By: Stephen Thomas <stephen.thomas@arm.com>
Co-Authored-By: Tejas Belagod <tejas.belagod@arm.com>
Co-Authored-By: Yufeng Zhang <yufeng.zhang@arm.com>
From-SVN: r192724
Diffstat (limited to 'gcc/doc/md.texi')
-rw-r--r-- | gcc/doc/md.texi | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 696ca94..88e1ca7 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -1671,6 +1671,66 @@ table heading for each architecture is the definitive reference for the meanings of that architecture's constraints. @table @emph +@item AArch64 family---@file{config/aarch64/constraints.md} +@table @code +@item k +The stack pointer register (@code{SP}) + +@item w +Floating point or SIMD vector register + +@item I +Integer constant that is valid as an immediate operand in an @code{ADD} +instruction + +@item J +Integer constant that is valid as an immediate operand in a @code{SUB} +instruction (once negated) + +@item K +Integer constant that can be used with a 32-bit logical instruction + +@item L +Integer constant that can be used with a 64-bit logical instruction + +@item M +Integer constant that is valid as an immediate operand in a 32-bit @code{MOV} +pseudo instruction. The @code{MOV} may be assembled to one of several different +machine instructions depending on the value + +@item N +Integer constant that is valid as an immediate operand in a 64-bit @code{MOV} +pseudo instruction + +@item S +An absolute symbolic address or a label reference + +@item Y +Floating point constant zero + +@item Z +Integer constant zero + +@item Usa +An absolute symbolic address + +@item Ush +The high part (bits 12 and upwards) of the pc-relative address of a symbol +within 4GB of the instruction + +@item Q +A memory address which uses a single base register with no offset + +@item Ump +A memory address suitable for a load/store pair instruction in SI, DI, SF and +DF modes + +@item Utf +A memory address suitable for a load/store pair instruction in TF mode + +@end table + + @item ARM family---@file{config/arm/constraints.md} @table @code @item w |