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| author | Kito Cheng <kito.cheng@sifive.com> | 2024-11-13 17:54:16 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2024-12-17 22:28:04 +0800 |
| commit | 46888571d242cf5623b7b0b74bb4490572f81cc9 (patch) | |
| tree | 7744e29df4eb09a42d57c8601dd435665ea259f5 /gcc/doc/md.texi | |
| parent | 1a2e0fcb857d82a7cb8909cf27a5dc833fecfa9a (diff) | |
| download | gcc-46888571d242cf5623b7b0b74bb4490572f81cc9.zip gcc-46888571d242cf5623b7b0b74bb4490572f81cc9.tar.gz gcc-46888571d242cf5623b7b0b74bb4490572f81cc9.tar.bz2 | |
RISC-V: Add cr and cf constraint
gcc/ChangeLog:
* config/riscv/constraints.md (cr): New.
(cf): New.
* config/riscv/riscv.h (reg_class): Add RVC_GR_REGS and
RVC_FP_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
* doc/md.texi: Document cr and cf constraint.
* config/riscv/riscv.cc (riscv_regno_to_class): Update
FP_REGS to RVC_FP_REGS since it smaller set.
(riscv_secondary_memory_needed): Handle RVC_FP_REGS.
(riscv_register_move_cost): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/constraint-cf-zfinx.c: New.
* gcc.target/riscv/constraint-cf.c: New.
* gcc.target/riscv/constraint-cr.c: New.
Diffstat (limited to 'gcc/doc/md.texi')
| -rw-r--r-- | gcc/doc/md.texi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 523ce9b..d5e5367 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3660,6 +3660,13 @@ A vector register, excluding v0 (if available). @item vm A vector register, only v0 (if available). +@item cr +RVC general purpose register (x8-x15). + +@item cf +RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when use +zfinx. + @end table @item RX---@file{config/rx/constraints.md} |