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authorWilco Dijkstra <wdijkstr@arm.com>2016-02-02 17:12:56 +0000
committerWilco Dijkstra <wilco@gcc.gnu.org>2016-02-02 17:12:56 +0000
commit31e2b5a3d8c539878f293fe30f1f7be7d2adb084 (patch)
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Improve TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS target hook.
Improve TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS target hook. It turns out there is another case where the register allocator uses the union of register classes without checking that the cost of the resulting register class is lower than both (see https://gcc.gnu.org/ml/gcc-patches/2015-12/msg01765.html ). This happens when the cost of the best and alternative class are both lower than the memory cost. In this case we typically end up with ALL_REGS as the allocno class, which almost invariably results in bad allocations with many redundant int<->FP moves (which are expensive on various cores). AArch64 is affected by this significantly due to supporting many scalar integer operations in SIMD. Currently the TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS hook forces the class to GENERAL_REGS if the allocno class is ALL_REGS and the register has an integer mode. This is bad if the best class happens to be FP_REGS. To handle this case as well, an extra argument is needed in the hook to pass the best class. If the allocno class is ALL_REGS, but the best class isn't, we use the best class instead (rather than using the mode to force to GENERAL_REGS or FP_REGS). Previously this might happen: r79: preferred FP_REGS, alternative GENERAL_REGS, allocno GENERAL_REGS a1 (r79,l0) best GENERAL_REGS, allocno GENERAL_REGS a1(r79,l0) costs: CALLER_SAVE_REGS:5000,5000 GENERAL_REGS:5000,5000 FP_LO_REGS:0,0 FP_REGS:0,0 ALL_REGS:10000,10000 MEM:9000,9000 The proposed allocno is ALL_REGS (despite having the highest cost!) and is then forced by the hook to GENERAL_REGS because r79 has integer mode. However FP_REGS has the lowest cost. After this patch the choice is as follows: r79: preferred FP_REGS, alternative GENERAL_REGS, allocno FP_REGS a1 (r79,l0) best FP_REGS, allocno FP_REGS As a result it is now no longer a requirement to use register move costs that are larger than the memory move cost. So it will be feasible to use realistic costs for both without a huge penalty. 2016-02-02 Wilco Dijkstra <wdijkstr@arm.com> gcc/ * ira-costs.c (find_costs_and_classes): Add extra argument. * target.def (ira_change_pseudo_allocno_class): Add parameter. * targhooks.h (ira_change_pseudo_allocno_class): Likewise. * targhooks.c (ira_change_pseudo_allocno_class): Likewise. * config/aarch64/aarch64.c (aarch64_ira_change_pseudo_allocno_class) Add best_class parameter, and return it if not ALL_REGS. * config/mips/mips.c (mips_ira_change_pseudo_allocno_class): Add parameter. * doc/tm.texi (TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS): Update target hook. From-SVN: r233084
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