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| author | Richard Sandiford <richard.sandiford@arm.com> | 2021-08-03 13:00:43 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2021-08-03 13:00:43 +0100 |
| commit | fa3ca6151ccac0e215727641eee36abf6e437b26 (patch) | |
| tree | 7e96fb523000964e55a9df863e7061ad1755242d /gcc/doc/invoke.texi | |
| parent | d0b952edd3f5753332ea234ef261711a81e87229 (diff) | |
| download | gcc-fa3ca6151ccac0e215727641eee36abf6e437b26.zip gcc-fa3ca6151ccac0e215727641eee36abf6e437b26.tar.gz gcc-fa3ca6151ccac0e215727641eee36abf6e437b26.tar.bz2 | |
aarch64: Turn sve_width tuning field into a bitmask
The tuning structures have an sve_width field that specifies the
number of bits in an SVE vector (or SVE_NOT_IMPLEMENTED if not
applicable). This patch turns the field into a bitmask so that
it can specify multiple widths at the same time. For now we
always treat the mininum width as the likely width.
An alternative would have been to add extra fields, which would
have coped correctly with non-power-of-2 widths. However,
we're very far from supporting constant non-power-of-2 vectors
in GCC, so I think the non-power-of-2 case will in reality always
have to be hidden behind VLA.
gcc/
* config/aarch64/aarch64-protos.h (tune_params::sve_width): Turn
into a bitmask.
* config/aarch64/aarch64.c (aarch64_cmp_autovec_modes): Update
accordingly.
(aarch64_estimated_poly_value): Likewise. Use the least significant
set bit for the minimum and likely values. Use the most significant
set bit for the maximum value.
Diffstat (limited to 'gcc/doc/invoke.texi')
0 files changed, 0 insertions, 0 deletions