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| author | Eric Botcazou <ebotcazou@adacore.com> | 2025-01-18 18:58:02 +0100 |
|---|---|---|
| committer | Eric Botcazou <ebotcazou@adacore.com> | 2025-01-18 19:03:47 +0100 |
| commit | d309844d6fe02e695eb82cbd30fd135e836f24eb (patch) | |
| tree | 7ae53dd209e169bba590071d5131f2f906333d18 /gcc/doc/invoke.texi | |
| parent | 729591f1017bf72f924d2bb6ebbad202da95171d (diff) | |
| download | gcc-d309844d6fe02e695eb82cbd30fd135e836f24eb.zip gcc-d309844d6fe02e695eb82cbd30fd135e836f24eb.tar.gz gcc-d309844d6fe02e695eb82cbd30fd135e836f24eb.tar.bz2 | |
Fix bootstrap failure on SPARC with -O3 -mcpu=niagara4
This is a regression present on the mainline only, but the underlying issue
has been latent for years: the compiler and the assembler disagree on the
support of the VIS 3B SIMD ISA, the former bundling it with VIS 3 but not
the latter. IMO the documentation is not very clear, so this patch just
aligns the compiler with the assembler.
gcc/
PR target/118512
* config/sparc/sparc-c.cc (sparc_target_macros): Deal with VIS 3B.
* config/sparc/sparc.cc (dump_target_flag_bits): Likewise.
(sparc_option_override): Likewise.
(sparc_vis_init_builtins): Likewise.
* config/sparc/sparc.md (fpcmp_vis): Replace TARGET_VIS3 with
TARGET_VIS3B.
(vec_cmp): Likewise.
(fpcmpu_vis): Likewise.
(vec_cmpu): Likewise.
(vcond_mask_): Likewise.
* config/sparc/sparc.opt (VIS3B): New target mask.
* doc/invoke.texi (SPARC options): Document -mvis3b.
gcc/testsuite/
* gcc.target/sparc/20230328-1.c: Pass -mvis3b instead of -mvis3.
* gcc.target/sparc/20230328-4.c: Likewise.
* gcc.target/sparc/fucmp.c: Likewise.
* gcc.target/sparc/vis3misc.c: Likewise.
Diffstat (limited to 'gcc/doc/invoke.texi')
| -rw-r--r-- | gcc/doc/invoke.texi | 22 |
1 files changed, 18 insertions, 4 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 9723d9c..7281104 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1412,7 +1412,8 @@ See RS/6000 and PowerPC Options. -munaligned-doubles -mno-unaligned-doubles -muser-mode -mno-user-mode -mv8plus -mno-v8plus -mvis -mno-vis --mvis2 -mno-vis2 -mvis3 -mno-vis3 +-mvis2 -mno-vis2 +-mvis3 -mno-vis3 -mvis3b -mno-vis3b -mvis4 -mno-vis4 -mvis4b -mno-vis4b -mcbcond -mno-cbcond -mfmaf -mno-fmaf -mfsmuld -mno-fsmuld -mpopc -mno-popc -msubxc -mno-subxc @@ -33843,6 +33844,18 @@ default is @option{-mvis3} when targeting a cpu that supports such instructions, such as niagara-3 and later. Setting @option{-mvis3} also sets @option{-mvis2} and @option{-mvis}. +@opindex mvis3b +@opindex mno-vis3b +@item -mvis3b +@itemx -mno-vis3b +With @option{-mvis3b}, GCC generates code that takes advantage of +version 3.0 of the UltraSPARC Visual Instruction Set extensions, plus +the additional VIS instructions introduced in the Oracle SPARC +Architecture 2011. The default is @option{-mvis3b} when targeting +a cpu that supports such instructions, such as niagara-7 and later. +Setting @option{-mvis3b} also sets @option{-mvis3}, @option{-mvis2} +and @option{-mvis}. + @opindex mvis4 @opindex mno-vis4 @item -mvis4 @@ -33851,7 +33864,8 @@ With @option{-mvis4}, GCC generates code that takes advantage of version 4.0 of the UltraSPARC Visual Instruction Set extensions. The default is @option{-mvis4} when targeting a cpu that supports such instructions, such as niagara-7 and later. Setting @option{-mvis4} -also sets @option{-mvis3}, @option{-mvis2} and @option{-mvis}. +also sets @option{-mvis3b}, @option{-mvis3}, @option{-mvis2} and +@option{-mvis}. @opindex mvis4b @opindex mno-vis4b @@ -33862,8 +33876,8 @@ version 4.0 of the UltraSPARC Visual Instruction Set extensions, plus the additional VIS instructions introduced in the Oracle SPARC Architecture 2017. The default is @option{-mvis4b} when targeting a cpu that supports such instructions, such as m8 and later. Setting -@option{-mvis4b} also sets @option{-mvis4}, @option{-mvis3}, -@option{-mvis2} and @option{-mvis}. +@option{-mvis4b} also sets @option{-mvis4}, @option{-mvis3b}, +@option{-mvis3}, @option{-mvis2} and @option{-mvis}. @opindex mcbcond @opindex mno-cbcond |