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| author | James Greenhalgh <james.greenhalgh@arm.com> | 2017-07-14 15:48:57 +0000 |
|---|---|---|
| committer | James Greenhalgh <jgreenhalgh@gcc.gnu.org> | 2017-07-14 15:48:57 +0000 |
| commit | 4ddf9709c585731e5a6f326ed4688a8d49510c66 (patch) | |
| tree | 4aaef92fb51f50d503a5d28cc39919c4ed982303 /gcc/doc/invoke.texi | |
| parent | 514b60f11b0397f57eeb79a6110f6ad7880500f5 (diff) | |
| download | gcc-4ddf9709c585731e5a6f326ed4688a8d49510c66.zip gcc-4ddf9709c585731e5a6f326ed4688a8d49510c66.tar.gz gcc-4ddf9709c585731e5a6f326ed4688a8d49510c66.tar.bz2 | |
[Patch ARM] Document the +crypto extension on CPUs.
We don't document the list of CPU names which can take a +crypto extension
in the ARM port. This patch fixes that oversight.
gcc/
2017-14-07 James Greenhalgh <james.greenhalgh@arm.com>
* doc/invoke.texi (arm/-mcpu): Document +crypto.
From-SVN: r250207
Diffstat (limited to 'gcc/doc/invoke.texi')
| -rw-r--r-- | gcc/doc/invoke.texi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 9cf85d1..b9d071b 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -15636,6 +15636,14 @@ on @samp{cortex-r5}, @samp{cortex-r52} and @samp{cortex-m7}. Disables the SIMD (but not floating-point) instructions on @samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7} and @samp{cortex-a9}. + +@item +crypto +Enables the cryptographic instructions on @samp{cortex-a32}, +@samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55}, @samp{cortex-a57}, +@samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75}, @samp{exynos-m1}, +@samp{xgene1}, @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}, +@samp{cortex-a73.cortex-a35}, @samp{cortex-a73.cortex-a53} and +@samp{cortex-a75.cortex-a55}. @end table Additionally the @samp{generic-armv7-a} pseudo target defaults to |