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authorHaochen Jiang <haochen.jiang@intel.com>2023-11-20 15:47:44 +0800
committerHaochen Jiang <haochen.jiang@intel.com>2023-11-20 15:47:44 +0800
commit2f8f7ee2db82a315f9faf8b306d6203ca7f7b002 (patch)
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parente85c596ae2d1e5f5b769b5af4c0a8e7d055e40d7 (diff)
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Initial support for AVX10.1
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Add avx10_set and version and detect avx10.1. (cpu_indicator_init): Handle avx10.1-512. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVX10_1_256_SET): New. (OPTION_MASK_ISA2_AVX10_1_256_SET): Ditto. (OPTION_MASK_ISA2_AVX10_1_512_UNSET): Ditto. (OPTION_MASK_ISA2_AVX10_1_512_UNSET): Ditto. (OPTION_MASK_ISA2_AVX2_UNSET): Modify for AVX10.1. (ix86_handle_option): Handle -mavx10.1-256 and -mavx10.1-512. Add indicator for explicit no-avx512 and no-avx10.1 options. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AVX10_1_256 and FEATURE_AVX10_1_512. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for AVX10_1_256 and AVX10_1_512. * config/i386/cpuid.h (bit_AVX10): New. (bit_AVX10_256): Ditto. (bit_AVX10_512): Ditto. * config/i386/driver-i386.cc (check_avx10_avx512_features): New. (host_detect_local_cpu): Do not append "-mno-" options under specific scenarios to avoid emitting a warning. * config/i386/i386-isa.def (EVEX512): Add DEF_PTA(EVEX512). (AVX10_1_256): Add DEF_PTA(AVX10_1_256). (AVX10_1_512): Add DEF_PTA(AVX10_1_512). * config/i386/i386-options.cc (isa2_opts): Add -mavx10.1-256 and -mavx10.1-512. (ix86_function_specific_save): Save explicit no indicator. (ix86_function_specific_restore): Restore explicit no indicator. (ix86_valid_target_attribute_inner_p): Handle avx10.1, avx10.1-256 and avx10.1-512. (ix86_valid_target_attribute_tree): Handle avx512 function attributes with avx10.1 command line option. (ix86_option_override_internal): Handle AVX10.1 options. * config/i386/i386.h: Add PTA_EVEX512 for AVX512 target machines. * config/i386/i386.opt: Add variable ix86_no_avx512_explicit and ix86_no_avx10_1_explicit, option -mavx10.1, -mavx10.1-256 and -mavx10.1-512. * doc/extend.texi: Document avx10.1, avx10.1-256 and avx10.1-512. * doc/invoke.texi: Document -mavx10.1, -mavx10.1-256 and -mavx10.1-512. * doc/sourcebuild.texi: Document target avx10.1, avx10.1-256 and avx10.1-512. gcc/testsuite/ChangeLog: * gcc.target/i386/avx10_1-1.c: New test. * gcc.target/i386/avx10_1-10.c: Ditto. * gcc.target/i386/avx10_1-11.c: Ditto. * gcc.target/i386/avx10_1-12.c: Ditto. * gcc.target/i386/avx10_1-13.c: Ditto. * gcc.target/i386/avx10_1-14.c: Ditto. * gcc.target/i386/avx10_1-15.c: Ditto. * gcc.target/i386/avx10_1-16.c: Ditto. * gcc.target/i386/avx10_1-17.c: Ditto. * gcc.target/i386/avx10_1-18.c: Ditto. * gcc.target/i386/avx10_1-19.c: Ditto. * gcc.target/i386/avx10_1-2.c: Ditto. * gcc.target/i386/avx10_1-20.c: Ditto. * gcc.target/i386/avx10_1-21.c: Ditto. * gcc.target/i386/avx10_1-22.c: Ditto. * gcc.target/i386/avx10_1-23.c: Ditto. * gcc.target/i386/avx10_1-3.c: Ditto. * gcc.target/i386/avx10_1-4.c: Ditto. * gcc.target/i386/avx10_1-5.c: Ditto. * gcc.target/i386/avx10_1-6.c: Ditto. * gcc.target/i386/avx10_1-7.c: Ditto. * gcc.target/i386/avx10_1-8.c: Ditto. * gcc.target/i386/avx10_1-9.c: Ditto.
Diffstat (limited to 'gcc/doc/invoke.texi')
-rw-r--r--gcc/doc/invoke.texi17
1 files changed, 13 insertions, 4 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 1f10967..bc9f4f7 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1453,7 +1453,7 @@ See RS/6000 and PowerPC Options.
-mamx-tile -mamx-int8 -mamx-bf16 -muintr -mhreset -mavxvnni
-mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16
-mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mapxf
--musermsr
+-musermsr -mavx10.1 -mavx10.1-256 -mavx10.1-512
-mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops
-minline-stringops-dynamically -mstringop-strategy=@var{alg}
-mkl -mwidekl
@@ -34123,6 +34123,15 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
@need 200
@opindex musermsr
@itemx -musermsr
+@need 200
+@opindex mavx10.1
+@itemx -mavx10.1
+@need 200
+@opindex mavx10.1-256
+@itemx -mavx10.1-256
+@need 200
+@opindex mavx10.1-512
+@itemx -mavx10.1-512
These switches enable the use of instructions in the MMX, SSE,
AVX512ER, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA,
AES, PCLMUL, CLFLUSHOPT, CLWB, FSGSBASE, PTWRITE, RDRND, F16C, FMA, PCONFIG,
@@ -34133,9 +34142,9 @@ GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16,
ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALIZE,
UINTR, HRESET, AMXTILE, AMXINT8, AMXBF16, KL, WIDEKL, AVXVNNI, AVX512-FP16,
AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AMX-FP16, PREFETCHI, RAOINT,
-AMX-COMPLEX, AVXVNNIINT16, SM3, SHA512, SM4, APX_F, USER_MSR or CLDEMOTE
-extended instruction sets. Each has a corresponding @option{-mno-} option
-to disable use of these instructions.
+AMX-COMPLEX, AVXVNNIINT16, SM3, SHA512, SM4, APX_F, USER_MSR, AVX10.1 or
+CLDEMOTE extended instruction sets. Each has a corresponding @option{-mno-}
+option to disable use of these instructions.
These extensions are also available as built-in functions: see
@ref{x86 Built-in Functions}, for details of the functions enabled and