Remove Cell Broadband Engine SPU targets

From-SVN: r275343

1 files changed, 0 insertions, 147 deletions

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index cfa3f86..2e353be 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1214,17 +1214,6 @@ See RS/6000 and PowerPC Options.
 -mfix-at697f  -mfix-ut699  -mfix-ut700  -mfix-gr712rc @gol
 -mlra  -mno-lra}
 
-@emph{SPU Options}
-@gccoptlist{-mwarn-reloc  -merror-reloc @gol
--msafe-dma  -munsafe-dma @gol
--mbranch-hints @gol
--msmall-mem  -mlarge-mem  -mstdmain @gol
--mfixed-range=@var{register-range} @gol
--mea32  -mea64 @gol
--maddress-space-conversion  -mno-address-space-conversion @gol
--mcache-size=@var{cache-size} @gol
--matomic-updates  -mno-atomic-updates}
-
 @emph{System V Options}
 @gccoptlist{-Qy  -Qn  -YP,@var{paths}  -Ym,@var{dir}}
 
@@ -15717,7 +15706,6 @@ platform.
 * SH Options::
 * Solaris 2 Options::
 * SPARC Options::
-* SPU Options::
 * System V Options::
 * TILE-Gx Options::
 * TILEPro Options::
@@ -26772,141 +26760,6 @@ when making stack frame references.  This is the default in 64-bit mode.
 Otherwise, assume no such offset is present.
 @end table
 
-@node SPU Options
-@subsection SPU Options
-@cindex SPU options
-
-These @samp{-m} options are supported on the SPU:
-
-@table @gcctabopt
-@item -mwarn-reloc
-@itemx -merror-reloc
-@opindex mwarn-reloc
-@opindex merror-reloc
-
-The loader for SPU does not handle dynamic relocations.  By default, GCC
-gives an error when it generates code that requires a dynamic
-relocation.  @option{-mno-error-reloc} disables the error,
-@option{-mwarn-reloc} generates a warning instead.
-
-@item -msafe-dma
-@itemx -munsafe-dma
-@opindex msafe-dma
-@opindex munsafe-dma
-
-Instructions that initiate or test completion of DMA must not be
-reordered with respect to loads and stores of the memory that is being
-accessed.
-With @option{-munsafe-dma} you must use the @code{volatile} keyword to protect
-memory accesses, but that can lead to inefficient code in places where the
-memory is known to not change.  Rather than mark the memory as volatile,
-you can use @option{-msafe-dma} to tell the compiler to treat
-the DMA instructions as potentially affecting all memory.  
-
-@item -mbranch-hints
-@opindex mbranch-hints
-
-By default, GCC generates a branch hint instruction to avoid
-pipeline stalls for always-taken or probably-taken branches.  A hint
-is not generated closer than 8 instructions away from its branch.
-There is little reason to disable them, except for debugging purposes,
-or to make an object a little bit smaller.
-
-@item -msmall-mem
-@itemx -mlarge-mem
-@opindex msmall-mem
-@opindex mlarge-mem
-
-By default, GCC generates code assuming that addresses are never larger
-than 18 bits.  With @option{-mlarge-mem} code is generated that assumes
-a full 32-bit address.
-
-@item -mstdmain
-@opindex mstdmain
-
-By default, GCC links against startup code that assumes the SPU-style
-main function interface (which has an unconventional parameter list).
-With @option{-mstdmain}, GCC links your program against startup
-code that assumes a C99-style interface to @code{main}, including a
-local copy of @code{argv} strings.
-
-@item -mfixed-range=@var{register-range}
-@opindex mfixed-range
-Generate code treating the given register range as fixed registers.
-A fixed register is one that the register allocator cannot use.  This is
-useful when compiling kernel code.  A register range is specified as
-two registers separated by a dash.  Multiple register ranges can be
-specified separated by a comma.
-
-@item -mea32
-@itemx -mea64
-@opindex mea32
-@opindex mea64
-Compile code assuming that pointers to the PPU address space accessed
-via the @code{__ea} named address space qualifier are either 32 or 64
-bits wide.  The default is 32 bits.  As this is an ABI-changing option,
-all object code in an executable must be compiled with the same setting.
-
-@item -maddress-space-conversion
-@itemx -mno-address-space-conversion
-@opindex maddress-space-conversion
-@opindex mno-address-space-conversion
-Allow/disallow treating the @code{__ea} address space as superset
-of the generic address space.  This enables explicit type casts
-between @code{__ea} and generic pointer as well as implicit
-conversions of generic pointers to @code{__ea} pointers.  The
-default is to allow address space pointer conversions.
-
-@item -mcache-size=@var{cache-size}
-@opindex mcache-size
-This option controls the version of libgcc that the compiler links to an
-executable and selects a software-managed cache for accessing variables
-in the @code{__ea} address space with a particular cache size.  Possible
-options for @var{cache-size} are @samp{8}, @samp{16}, @samp{32}, @samp{64}
-and @samp{128}.  The default cache size is 64KB.
-
-@item -matomic-updates
-@itemx -mno-atomic-updates
-@opindex matomic-updates
-@opindex mno-atomic-updates
-This option controls the version of libgcc that the compiler links to an
-executable and selects whether atomic updates to the software-managed
-cache of PPU-side variables are used.  If you use atomic updates, changes
-to a PPU variable from SPU code using the @code{__ea} named address space
-qualifier do not interfere with changes to other PPU variables residing
-in the same cache line from PPU code.  If you do not use atomic updates,
-such interference may occur; however, writing back cache lines is
-more efficient.  The default behavior is to use atomic updates.
-
-@item -mdual-nops
-@itemx -mdual-nops=@var{n}
-@opindex mdual-nops
-By default, GCC inserts NOPs to increase dual issue when it expects
-it to increase performance.  @var{n} can be a value from 0 to 10.  A
-smaller @var{n} inserts fewer NOPs.  10 is the default, 0 is the
-same as @option{-mno-dual-nops}.  Disabled with @option{-Os}.
-
-@item -mhint-max-nops=@var{n}
-@opindex mhint-max-nops
-Maximum number of NOPs to insert for a branch hint.  A branch hint must
-be at least 8 instructions away from the branch it is affecting.  GCC
-inserts up to @var{n} NOPs to enforce this, otherwise it does not
-generate the branch hint.
-
-@item -mhint-max-distance=@var{n}
-@opindex mhint-max-distance
-The encoding of the branch hint instruction limits the hint to be within
-256 instructions of the branch it is affecting.  By default, GCC makes
-sure it is within 125.
-
-@item -msafe-hints
-@opindex msafe-hints
-Work around a hardware bug that causes the SPU to stall indefinitely.
-By default, GCC inserts the @code{hbrp} instruction to make sure
-this stall won't happen.
-
-@end table
-
 @node System V Options
 @subsection Options for System V