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| author | Uros Bizjak <ubizjak@gmail.com> | 2024-05-31 15:52:03 +0200 |
|---|---|---|
| committer | Uros Bizjak <ubizjak@gmail.com> | 2024-05-31 15:52:03 +0200 |
| commit | 0ac802064c2a018cf166c37841697e867de65a95 (patch) | |
| tree | 8aa0dc39d0a12818bf410896d7ccbea4ffa82e37 /gcc/doc/extend.texi | |
| parent | d9c90c82d900fdae95df4499bf5f0a4ecb903b53 (diff) | |
| download | gcc-0ac802064c2a018cf166c37841697e867de65a95.zip gcc-0ac802064c2a018cf166c37841697e867de65a95.tar.gz gcc-0ac802064c2a018cf166c37841697e867de65a95.tar.bz2 | |
alpha: Fix invalid RTX in divmodsi insn patterns [PR115297]
any_divmod instructions are modelled with invalid RTX:
[(set (match_operand:DI 0 "register_operand" "=c")
(sign_extend:DI (match_operator:SI 3 "divmod_operator"
[(match_operand:DI 1 "register_operand" "a")
(match_operand:DI 2 "register_operand" "b")])))
(clobber (reg:DI 23))
(clobber (reg:DI 28))]
where SImode divmod_operator (div,mod,udiv,umod) has DImode operands.
Wrap input operand with truncate:SI to make machine modes consistent.
PR target/115297
gcc/ChangeLog:
* config/alpha/alpha.md (<any_divmod:code>si3): Wrap DImode
operands 3 and 4 with truncate:SI RTX.
(*divmodsi_internal_er): Ditto for operands 1 and 2.
(*divmodsi_internal_er_1): Ditto.
(*divmodsi_internal): Ditto.
* config/alpha/constraints.md ("b"): Correct register
number in the description.
gcc/testsuite/ChangeLog:
* gcc.target/alpha/pr115297.c: New test.
Diffstat (limited to 'gcc/doc/extend.texi')
0 files changed, 0 insertions, 0 deletions