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authorSandra Loosemore <sandra@codesourcery.com>2010-07-02 20:31:43 -0400
committerSandra Loosemore <sandra@gcc.gnu.org>2010-07-02 20:31:43 -0400
commitbab53516d0a58120f1d3b24aabc09a3d7e6443aa (patch)
tree716708677aed26e5c65cf3ff167cec3906175513 /gcc/doc/arm-neon-intrinsics.texi
parentb614e5669ebff10b7ec9b5fff4e539ab1416e38b (diff)
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neon.md (UNSPEC_VABA): Delete.
2010-07-02 Sandra Loosemore <sandra@codesourcery.com> Julian Brown <julian@codesourcery.com> gcc/ * config/arm/neon.md (UNSPEC_VABA): Delete. (UNSPEC_VABAL): Delete. (UNSPEC_VABS): Delete. (UNSPEC_VMUL_N): Delete. (adddi3_neon): New. (subdi3_neon): New. (mul<mode>3add<mode>_neon): Make the pattern named. (mul<mode>3neg<mode>add<mode>_neon): Likewise. (neon_vadd<mode>): Replace with define_expand, and move the remaining unspec parts... (neon_vadd<mode>_unspec): ...to this. (neon_vmla<mode>, neon_vmla<mode>_unspec): Likewise. (neon_vlms<mode>, neon_vmls<mode>_unspec): Likewise. (neon_vsub<mode>, neon_vsub<mode>_unspec): Likewise. (neon_vaba<mode>): Rewrite in terms of vabd. (neon_vabal<mode>): Rewrite in terms of vabdl. (neon_vabs<mode>): Rewrite without unspec. * config/arm/arm.md (*arm_adddi3): Disable for TARGET_NEON. (*arm_subdi3): Likewise. * config/arm/neon.ml (Vadd, Vsub): Split out 64-bit variants and add No_op attribute to disable assembly output checks. * config/arm/arm_neon.h: Regenerated. * doc/arm-neon-intrinsics.texi: Regenerated. gcc/testsuite/ * gcc.target/arm/neon/vadds64.c: Regenerated. * gcc.target/arm/neon/vaddu64.c: Regenerated. * gcc.target/arm/neon/vsubs64.c: Regenerated. * gcc.target/arm/neon/vsubu64.c: Regenerated. * gcc.target/arm/neon-vmla-1.c: Add -ffast-math to options. * gcc.target/arm/neon-vmls-1.c: Likewise. * gcc.target/arm/neon-vsubs64.c: New execution test. * gcc.target/arm/neon-vsubu64.c: New execution test. * gcc.target/arm/neon-vadds64.c: New execution test. * gcc.target/arm/neon-vaddu64.c: New execution test. Co-Authored-By: Julian Brown <julian@codesourcery.com> From-SVN: r161762
Diffstat (limited to 'gcc/doc/arm-neon-intrinsics.texi')
-rw-r--r--gcc/doc/arm-neon-intrinsics.texi20
1 files changed, 8 insertions, 12 deletions
diff --git a/gcc/doc/arm-neon-intrinsics.texi b/gcc/doc/arm-neon-intrinsics.texi
index d21fabd..a75e582 100644
--- a/gcc/doc/arm-neon-intrinsics.texi
+++ b/gcc/doc/arm-neon-intrinsics.texi
@@ -43,20 +43,18 @@
@itemize @bullet
-@item uint64x1_t vadd_u64 (uint64x1_t, uint64x1_t)
-@*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{d0}, @var{d0}, @var{d0}}
+@item float32x2_t vadd_f32 (float32x2_t, float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{d0}, @var{d0}, @var{d0}}
@end itemize
@itemize @bullet
-@item int64x1_t vadd_s64 (int64x1_t, int64x1_t)
-@*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{d0}, @var{d0}, @var{d0}}
+@item uint64x1_t vadd_u64 (uint64x1_t, uint64x1_t)
@end itemize
@itemize @bullet
-@item float32x2_t vadd_f32 (float32x2_t, float32x2_t)
-@*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{d0}, @var{d0}, @var{d0}}
+@item int64x1_t vadd_s64 (int64x1_t, int64x1_t)
@end itemize
@@ -1013,20 +1011,18 @@
@itemize @bullet
-@item uint64x1_t vsub_u64 (uint64x1_t, uint64x1_t)
-@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{d0}, @var{d0}, @var{d0}}
+@item float32x2_t vsub_f32 (float32x2_t, float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{d0}, @var{d0}, @var{d0}}
@end itemize
@itemize @bullet
-@item int64x1_t vsub_s64 (int64x1_t, int64x1_t)
-@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{d0}, @var{d0}, @var{d0}}
+@item uint64x1_t vsub_u64 (uint64x1_t, uint64x1_t)
@end itemize
@itemize @bullet
-@item float32x2_t vsub_f32 (float32x2_t, float32x2_t)
-@*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{d0}, @var{d0}, @var{d0}}
+@item int64x1_t vsub_s64 (int64x1_t, int64x1_t)
@end itemize