LoongArch: Mask shift offset when emit {xv, v}{srl, sll, sra} with sameimm vector

For {xv,v}{srl,sll,sra}, the constraint `vector_same_uimm6` cause overflow
in when emit {w,h,b}. Since the number of bits shifted is the remainder of
the register value, it is actually unnecessary to constrain the range.
Simply mask the shift number with the unit-bit-width, without any
constraint on the shift range.

gcc/ChangeLog:

	* config/loongarch/constraints.md (Uuv6, Uuvx): Remove Uuv6,
	add Uuvx as replicated vector const with unsigned range [0,umax].
	* config/loongarch/lasx.md (xvsrl, xvsra, xvsll): Mask shift
	offset by its unit bits.
	* config/loongarch/lsx.md (vsrl, vsra, vsll): Likewise.
	* config/loongarch/loongarch-protos.h
	(loongarch_const_vector_same_int_p): Set default for low and high.
	* config/loongarch/predicates.md: Replace reg_or_vector_same_uimm6
	_operand to reg_or_vector_same_uimm_operand.

gcc/testsuite/ChangeLog:

	* gcc.target/loongarch/vector/lasx/lasx-shift-sameimm-vec.c: New test.
	* gcc.target/loongarch/vector/lsx/lsx-shift-sameimm-vec.c: New test.

0 files changed, 0 insertions, 0 deletions