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| author | Xi Ruoyao <xry111@xry111.site> | 2023-12-30 21:40:11 +0800 |
|---|---|---|
| committer | Xi Ruoyao <xry111@xry111.site> | 2024-01-03 18:23:48 +0800 |
| commit | 87acfc36194e3101b8ebcc599a78e2481224922d (patch) | |
| tree | d18c20be443c2554c4f994508054ec440cc4c4b0 /gcc/d | |
| parent | a43bd8255451227fc1cd3601b1f0265b21fafada (diff) | |
| download | gcc-87acfc36194e3101b8ebcc599a78e2481224922d.zip gcc-87acfc36194e3101b8ebcc599a78e2481224922d.tar.gz gcc-87acfc36194e3101b8ebcc599a78e2481224922d.tar.bz2 | |
LoongArch: Provide fmin/fmax RTL pattern for vectors
We already had smin/smax RTL pattern using vfmin/vfmax instructions.
But for smin/smax, it's unspecified what will happen if either operand
contains any NaN operands. So we would not vectorize the loop with
-fno-finite-math-only (the default for all optimization levels expect
-Ofast).
But, LoongArch vfmin/vfmax instruction is IEEE-754-2008 conformant so we
can also use them and vectorize the loop.
gcc/ChangeLog:
* config/loongarch/simd.md (fmax<mode>3): New define_insn.
(fmin<mode>3): Likewise.
(reduc_fmax_scal_<mode>3): New define_expand.
(reduc_fmin_scal_<mode>3): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/vfmax-vfmin.c: New test.
Diffstat (limited to 'gcc/d')
0 files changed, 0 insertions, 0 deletions