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| author | Jeff Law <jlaw@ventanamicro.com> | 2024-08-25 07:16:50 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2024-08-25 07:16:50 -0600 |
| commit | 4c3485897d3e28ecfbe911f21f83fa047ee8b54b (patch) | |
| tree | 8ec86113e96dbe0d77111b927fbe0d049c171d3c /gcc/cppbuiltin.h | |
| parent | ab9c4bb54e817948f1a55edfb0f1f0481e4046df (diff) | |
| download | gcc-4c3485897d3e28ecfbe911f21f83fa047ee8b54b.zip gcc-4c3485897d3e28ecfbe911f21f83fa047ee8b54b.tar.gz gcc-4c3485897d3e28ecfbe911f21f83fa047ee8b54b.tar.bz2 | |
[committed] Fix assembly scan for RISC-V VLS tests
Surya's IRA patch from June slightly improves the code we generate for the
vls/calling-conventions tests on RISC-V. Specifically it removes an
unnecessary move from the instruction stream. This (of course) broke those
tests:
> Running /home/jlaw/test/gcc/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp ...
> FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c -O3 -ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times mv\\s+s0,a0\\s+call\\s+memset\\s+mv\\s+a0,s0 3
> FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c -O3 -ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times mv\\s+s0,a0\\s+call\\s+memset\\s+mv\\s+a0,s0 3
> FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c -O3 -ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times mv\\s+s0,a0\\s+call\\s+memset\\s+mv\\s+a0,s0 3
> FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c -O3 -ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times mv\\s+s0,a0\\s+call\\s+memset\\s+mv\\s+a0,s0 3
> FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c -O3 -ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times mv\\s+s0,a0\\s+call\\s+memset\\s+mv\\s+a0,s0 3
> FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c -O3 -ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times mv\\s+s0,a0\\s+call\\s+memset\\s+mv\\s+a0,s0 3
> FAIL: gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c -O3 -ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times mv\\s+s0,a0\\s+call\\s+memset\\s+mv\\s+a0,s0 3
This patch does the natural adjustment of those tests by dropping the moves
from the scan.
gcc/testsuite
* gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: Update
expected output.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: Likewise.
* gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: Likewise.
Diffstat (limited to 'gcc/cppbuiltin.h')
0 files changed, 0 insertions, 0 deletions