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author | Pan Li <pan2.li@intel.com> | 2024-08-17 09:25:58 -0600 |
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committer | Jeff Law <jlaw@ventanamicro.com> | 2024-08-17 09:25:58 -0600 |
commit | 06ae7bc1345a31a5f23dc86b348a1bef59bb3cc1 (patch) | |
tree | 3c438c0663db0365b8086a232599265c5fcad55e /gcc/coverage.c | |
parent | 54b228d80c54d32ab49cee6148cfd1364b2bc817 (diff) | |
download | gcc-06ae7bc1345a31a5f23dc86b348a1bef59bb3cc1.zip gcc-06ae7bc1345a31a5f23dc86b348a1bef59bb3cc1.tar.gz gcc-06ae7bc1345a31a5f23dc86b348a1bef59bb3cc1.tar.bz2 |
RISC-V: Bugfix incorrect operand for vwsll auto-vect
This patch would like to fix one ICE when rv64gcv_zvbb for vwsll.
Consider below example.
void vwsll_vv_test (short *restrict dst, char *restrict a,
int *restrict b, int n)
{
for (int i = 0; i < n; i++)
dst[i] = a[i] << b[i];
}
It will hit the vwsll pattern with following operands.
operand 0 -> (reg:RVVMF2HI 146 [ vect__7.13 ])
operand 1 -> (reg:RVVMF4QI 165 [ vect_cst__33 ])
operand 2 -> (reg:RVVM1SI 171 [ vect_cst__36 ])
According to the ISA, operand 2 should be the same as operand 1.
Aka operand 2 should have RVVMF4QI mode as above. Thus, add
quad truncation for operand 2 before emit vwsll.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
PR target/116280
gcc/ChangeLog:
* config/riscv/autovec-opt.md: Add quad truncation to
align the mode requirement for vwsll.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr116280-1.c: New test.
* gcc.target/riscv/rvv/base/pr116280-2.c: New test.
Diffstat (limited to 'gcc/coverage.c')
0 files changed, 0 insertions, 0 deletions