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| author | Max Filippov <jcmvbkbc@gmail.com> | 2024-03-14 04:20:36 -0700 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2024-03-14 10:27:08 -0700 |
| commit | bc5a9dab55d13f888a3cdd150c8cf5c2244f35e0 (patch) | |
| tree | d842ce601776c19c1f10ec60f7dda288c63fe806 /gcc/config/xtensa | |
| parent | f89cfdb2f2e9b4fe517b1e00511c4d70a7014cbc (diff) | |
| download | gcc-bc5a9dab55d13f888a3cdd150c8cf5c2244f35e0.zip gcc-bc5a9dab55d13f888a3cdd150c8cf5c2244f35e0.tar.gz gcc-bc5a9dab55d13f888a3cdd150c8cf5c2244f35e0.tar.bz2 | |
gcc: xtensa: reorder movsi_internal patterns for better code generation during LRA
After switching to LRA xtensa backend generates the following code for
saving/loading registers:
movi a9, 0x190
add a9, a9, sp
s32i.n a3, a9, 0
instead of the shorter and more efficient
s32i a3, a9, 0x190
E.g. the following code can be used to reproduce it:
int f1(int a, int b, int c, int d, int e, int f, int *p);
int f2(int a, int b, int c, int d, int e, int f, int *p);
int f3(int a, int b, int c, int d, int e, int f, int *p);
int foo(int a, int b, int c, int d, int e, int f)
{
int g[100];
return
f1(a, b, c, d, e, f, g) +
f2(a, b, c, d, e, f, g) +
f3(a, b, c, d, e, f, g);
}
This happens in the LRA pass because s32i.n and l32i.n are listed before
the s32i and l32i in the movsi_internal pattern and alternative
consideration loop stops early.
gcc/
* config/xtensa/xtensa.md (movsi_internal): Move l32i and s32i
patterns ahead of the l32i.n and s32i.n.
Diffstat (limited to 'gcc/config/xtensa')
| -rw-r--r-- | gcc/config/xtensa/xtensa.md | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index 1a2249b..5cdf4df 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -1270,13 +1270,15 @@ }) (define_insn "movsi_internal" - [(set (match_operand:SI 0 "nonimmed_operand" "=D,D,D,D,R,R,a,q,a,a,W,a,a,U,*a,*A") - (match_operand:SI 1 "move_operand" "M,D,d,R,D,d,r,r,I,Y,i,T,U,r,*A,*r"))] + [(set (match_operand:SI 0 "nonimmed_operand" "=D,D,D,a,U,D,R,R,a,q,a,a,W,a,*a,*A") + (match_operand:SI 1 "move_operand" "M,D,d,U,r,R,D,d,r,r,I,Y,i,T,*A,*r"))] "xtensa_valid_move (SImode, operands)" "@ movi.n\t%0, %x1 mov.n\t%0, %1 mov.n\t%0, %1 + %v1l32i\t%0, %1 + %v0s32i\t%1, %0 %v1l32i.n\t%0, %1 %v0s32i.n\t%1, %0 %v0s32i.n\t%1, %0 @@ -1286,13 +1288,11 @@ movi\t%0, %1 const16\t%0, %t1\;const16\t%0, %b1 %v1l32r\t%0, %1 - %v1l32i\t%0, %1 - %v0s32i\t%1, %0 rsr\t%0, ACCLO wsr\t%1, ACCLO" - [(set_attr "type" "move,move,move,load,store,store,move,move,move,move,move,load,load,store,rsr,wsr") + [(set_attr "type" "move,move,move,load,store,load,store,store,move,move,move,move,move,load,rsr,wsr") (set_attr "mode" "SI") - (set_attr "length" "2,2,2,2,2,2,3,3,3,3,6,3,3,3,3,3")]) + (set_attr "length" "2,2,2,3,3,2,2,2,3,3,3,3,6,3,3,3")]) (define_split [(set (match_operand:SHI 0 "register_operand") |