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authorTakayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>2024-03-22 08:36:30 +0900
committerMax Filippov <jcmvbkbc@gmail.com>2024-03-22 18:12:18 -0700
commit7a01cc711f33530436712a5bfd18f8457a68ea1f (patch)
tree865475bdb741c184c1acd9356123bdbe2eed0f7c /gcc/config/xtensa
parente8985864a385992aa26e7c8373faa190e2ced17d (diff)
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xtensa: Add supplementary split pattern for "*addsubx"
int test(int a) { return a * 4 + 30000; } In the example above, since Xtensa has instructions to add register value scaled by 2, 4 or 8 (and corresponding define_insns), we would expect them to be used but not, because it is transformed before reaching the RTL generation pass as below: int test(int a) { return (a + 7500) * 4; } Fortunately, the RTL combination pass tries a splitting pattern that matches the first example, so it is easy to solve by defining that pattern. gcc/ChangeLog: * config/xtensa/xtensa.md: Add new split pattern described above.
Diffstat (limited to 'gcc/config/xtensa')
-rw-r--r--gcc/config/xtensa/xtensa.md14
1 files changed, 14 insertions, 0 deletions
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index 5cdf4df..fbe40ec 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -194,6 +194,20 @@
(set_attr "mode" "SI")
(set_attr "length" "3")])
+(define_split
+ [(set (match_operand:SI 0 "register_operand")
+ (plus:SI (ashift:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 3 "addsubx_operand"))
+ (match_operand:SI 2 "const_int_operand")))]
+ "TARGET_ADDX && can_create_pseudo_p ()"
+ [(set (match_dup 0)
+ (plus:SI (ashift:SI (match_dup 1)
+ (match_dup 3))
+ (match_dup 2)))]
+{
+ operands[2] = force_reg (SImode, operands[2]);
+})
+
(define_expand "adddi3"
[(set (match_operand:DI 0 "register_operand")
(plus:DI (match_operand:DI 1 "register_operand")