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| author | Nick Clifton <nickc@gcc.gnu.org> | 2013-04-03 14:06:38 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@gcc.gnu.org> | 2013-04-03 14:06:38 +0000 |
| commit | 4d85233e76d774a892dc812eaf532db768982fdc (patch) | |
| tree | 2e4ae4cd7a1e696685354b99b1d1bea89279e846 /gcc/config/v850 | |
| parent | 1b2253d4f89a5e605455a0a3a9d0e18b9b3537a0 (diff) | |
| download | gcc-4d85233e76d774a892dc812eaf532db768982fdc.zip gcc-4d85233e76d774a892dc812eaf532db768982fdc.tar.gz gcc-4d85233e76d774a892dc812eaf532db768982fdc.tar.bz2 | |
v850e3v5.md (fmasf4): Use fmaf.s on E3V5 architectures.
* config/v850/v850e3v5.md (fmasf4): Use fmaf.s on E3V5
architectures.
(fmssf4): Use fmsf.s on E3V5 architectures.
(fnmasf4): Use fnmaf.s on E3V5 architectures.
(fnmssf4): Use fnmsf.s on E3V5 architectures.
From-SVN: r197413
Diffstat (limited to 'gcc/config/v850')
| -rw-r--r-- | gcc/config/v850/v850.md | 22 |
1 files changed, 13 insertions, 9 deletions
diff --git a/gcc/config/v850/v850.md b/gcc/config/v850/v850.md index 4ed0e40..a074f65 100644 --- a/gcc/config/v850/v850.md +++ b/gcc/config/v850/v850.md @@ -2508,14 +2508,18 @@ (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) +;; Note: The FPU-2.0 (ie pre e3v5) versions of these routines do not actually +;; need operand 4 to be the same as operand 0. But the FPU-2.0 versions are +;; also deprecated so the loss of flexibility is unimportant. + ;;; multiply-add (define_insn "fmasf4" [(set (match_operand:SF 0 "register_operand" "=r") (fma:SF (match_operand:SF 1 "register_operand" "r") (match_operand:SF 2 "register_operand" "r") - (match_operand:SF 3 "register_operand" "r")))] + (match_operand:SF 3 "register_operand" "0")))] "TARGET_USE_FPU" - "maddf.s %2,%1,%3,%0" + { return TARGET_V850E3V5_UP ? "fmaf.s %1, %2, %0" : "maddf.s %2, %1, %3, %0"; } [(set_attr "length" "4") (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) @@ -2525,9 +2529,9 @@ [(set (match_operand:SF 0 "register_operand" "=r") (fma:SF (match_operand:SF 1 "register_operand" "r") (match_operand:SF 2 "register_operand" "r") - (neg:SF (match_operand:SF 3 "register_operand" "r"))))] + (neg:SF (match_operand:SF 3 "register_operand" "0"))))] "TARGET_USE_FPU" - "msubf.s %2,%1,%3,%0" + { return TARGET_V850E3V5_UP ? "fmsf.s %1, %2, %0" : "msubf.s %2, %1, %3, %0"; } [(set_attr "length" "4") (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) @@ -2537,21 +2541,21 @@ [(set (match_operand:SF 0 "register_operand" "=r") (neg:SF (fma:SF (match_operand:SF 1 "register_operand" "r") (match_operand:SF 2 "register_operand" "r") - (match_operand:SF 3 "register_operand" "r"))))] + (match_operand:SF 3 "register_operand" "0"))))] "TARGET_USE_FPU" - "nmaddf.s %2,%1,%3,%0" + { return TARGET_V850E3V5_UP ? "fnmaf.s %1, %2, %0" : "nmaddf.s %2, %1, %3, %0"; } [(set_attr "length" "4") (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) ;; negative-multiply-subtract (define_insn "fnmssf4" - [(set (match_operand:SF 0 "register_operand" "=r") + [(set (match_operand:SF 0 "register_operand" "=r") (neg:SF (fma:SF (match_operand:SF 1 "register_operand" "r") (match_operand:SF 2 "register_operand" "r") - (neg:SF (match_operand:SF 3 "register_operand" "r")))))] + (neg:SF (match_operand:SF 3 "register_operand" "0")))))] "TARGET_USE_FPU" - "nmsubf.s %2,%1,%3,%0" + { return TARGET_V850E3V5_UP ? "fnmsf.s %1, %2, %0" : "nmsubf.s %2, %1, %3, %0"; } [(set_attr "length" "4") (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) |