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authorDavid S. Miller <davem@davemloft.net>2012-02-21 01:37:42 +0000
committerDavid S. Miller <davem@gcc.gnu.org>2012-02-20 17:37:42 -0800
commit3ed27cf5e7f7507dc3fec0e6ad20aab55316cb57 (patch)
tree38e311a21b0073a0e3017df93bfd40876aa40ba6 /gcc/config/sparc
parentd1d7a85e534f4c388c881652f04bfe73ff71267c (diff)
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Explain why we don't use RDPC for sparc PIC register setup.
* config/sparc/sparc.md (load_pcrel_sym<P:mode>): Explain why we don't use the "rd %pc" instruction on v9 for PIC register loads. From-SVN: r184422
Diffstat (limited to 'gcc/config/sparc')
-rw-r--r--gcc/config/sparc/sparc.md4
1 files changed, 4 insertions, 0 deletions
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index f70acd3..c0c1ef8 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -1352,6 +1352,10 @@
;; Load in operand 0 the (absolute) address of operand 1, which is a symbolic
;; value subject to a PC-relative relocation. Operand 2 is a helper function
;; that adds the PC value at the call point to register #(operand 3).
+;;
+;; Even on V9 we use this call sequence with a stub, instead of "rd %pc, ..."
+;; because the RDPC instruction is extremely expensive and incurs a complete
+;; instruction pipeline flush.
(define_insn "load_pcrel_sym<P:mode>"
[(set (match_operand:P 0 "register_operand" "=r")