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| author | David S. Miller <davem@pierdol.cobaltmicro.com> | 1998-07-14 00:18:57 +0000 |
|---|---|---|
| committer | David S. Miller <davem@gcc.gnu.org> | 1998-07-13 17:18:57 -0700 |
| commit | 1c44748c3f81d776ccbf03371967fbd2b3014d1c (patch) | |
| tree | 16696438677f51ccc81bb930a154c2c7c37745fa /gcc/config/sparc | |
| parent | e8d1616611c860c5bcf8290999014a5cdaf24c19 (diff) | |
| download | gcc-1c44748c3f81d776ccbf03371967fbd2b3014d1c.zip gcc-1c44748c3f81d776ccbf03371967fbd2b3014d1c.tar.gz gcc-1c44748c3f81d776ccbf03371967fbd2b3014d1c.tar.bz2 | |
Fix regressions introduced by most recent Sparc commits.
Fix regressions introduced by most recent Sparc
commits.
* config/sparc/sparc.c (output_scc_insn): Enclose || conditions in
parens while walking over notes.
* config/sparc/sparc.md (reg movdi split): Clean up matching
conditions.
(all DI arithop splits on 32-bit): Handle immediate arguments
correctly when they are CONST_INTs.
From-SVN: r21127
Diffstat (limited to 'gcc/config/sparc')
| -rw-r--r-- | gcc/config/sparc/sparc.c | 2 | ||||
| -rw-r--r-- | gcc/config/sparc/sparc.md | 74 |
2 files changed, 55 insertions, 21 deletions
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index d45295f..da7c257 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -2736,7 +2736,7 @@ output_scc_insn (operands, insn) label = next; next = NEXT_INSN (next); } - while (next && GET_CODE (next) == NOTE || GET_CODE (next) == CODE_LABEL); + while (next && (GET_CODE (next) == NOTE || GET_CODE (next) == CODE_LABEL)); if (next && GET_CODE (next) == JUMP_INSN && simplejump_p (next)) label = JUMP_LABEL (next); diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index 156c086..47d2d3d 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -2260,8 +2260,9 @@ (define_split [(set (match_operand:DI 0 "register_operand" "=r") (match_operand:DI 1 "arith_double_operand" "rIN"))] - "! TARGET_ARCH64 && GET_CODE (operands[1]) == REG && REGNO (operands[0]) < 32 - && (GET_CODE (operands[1]) != REG || REGNO (operands[1]) < 32) + "! TARGET_ARCH64 + && REGNO (operands[0]) < 32 + && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32 && ! reg_overlap_mentioned_p (operands[0], operands[1])" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 5))] @@ -3723,12 +3724,23 @@ return \"srl %1,0,%0\"; (plus:SI (plus:SI (match_dup 7) (match_dup 8)) (ltu:SI (reg:CC_NOOV 100) (const_int 0))))] - "operands[3] = gen_lowpart (SImode, operands[0]); - operands[4] = gen_lowpart (SImode, operands[1]); - operands[5] = gen_lowpart (SImode, operands[2]); - operands[6] = gen_highpart (SImode, operands[0]); - operands[7] = gen_highpart (SImode, operands[1]); - operands[8] = gen_highpart (SImode, operands[2]);") + " +{ + operands[3] = gen_lowpart (SImode, operands[0]); + operands[4] = gen_lowpart (SImode, operands[1]); + operands[5] = gen_lowpart (SImode, operands[2]); + operands[6] = gen_highpart (SImode, operands[0]); + operands[7] = gen_highpart (SImode, operands[1]); + if (GET_CODE (operands[2]) == CONST_INT) + { + if (INTVAL (operands[2]) < 0) + operands[8] = constm1_rtx; + else + operands[8] = const0_rtx; + } + else + operands[8] = gen_highpart (SImode, operands[2]); +}") (define_split [(set (match_operand:DI 0 "register_operand" "=r") @@ -3746,12 +3758,23 @@ return \"srl %1,0,%0\"; (minus:SI (minus:SI (match_dup 7) (match_dup 8)) (ltu:SI (reg:CC_NOOV 100) (const_int 0))))] - "operands[3] = gen_lowpart (SImode, operands[0]); - operands[4] = gen_lowpart (SImode, operands[1]); - operands[5] = gen_lowpart (SImode, operands[2]); - operands[6] = gen_highpart (SImode, operands[0]); - operands[7] = gen_highpart (SImode, operands[1]); - operands[8] = gen_highpart (SImode, operands[2]);") + " +{ + operands[3] = gen_lowpart (SImode, operands[0]); + operands[4] = gen_lowpart (SImode, operands[1]); + operands[5] = gen_lowpart (SImode, operands[2]); + operands[6] = gen_highpart (SImode, operands[0]); + operands[7] = gen_highpart (SImode, operands[1]); + if (GET_CODE (operands[2]) == CONST_INT) + { + if (INTVAL (operands[2]) < 0) + operands[8] = constm1_rtx; + else + operands[8] = const0_rtx; + } + else + operands[8] = gen_highpart (SImode, operands[2]); +}") ;; LTU here means "carry set" (define_insn "*addx" @@ -4563,12 +4586,23 @@ return \"srl %1,0,%0\"; && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32" [(set (match_dup 4) (match_op_dup:SI 1 [(match_dup 6) (match_dup 8)])) (set (match_dup 5) (match_op_dup:SI 1 [(match_dup 7) (match_dup 9)]))] - "operands[4] = gen_highpart (SImode, operands[0]); - operands[5] = gen_lowpart (SImode, operands[0]); - operands[6] = gen_highpart (SImode, operands[2]); - operands[7] = gen_lowpart (SImode, operands[2]); - operands[8] = gen_highpart (SImode, operands[3]); - operands[9] = gen_lowpart (SImode, operands[3]);") + " +{ + operands[4] = gen_highpart (SImode, operands[0]); + operands[5] = gen_lowpart (SImode, operands[0]); + operands[6] = gen_highpart (SImode, operands[2]); + operands[7] = gen_lowpart (SImode, operands[2]); + if (GET_CODE (operands[3]) == CONST_INT) + { + if (INTVAL (operands[3]) < 0) + operands[8] = constm1_rtx; + else + operands[8] = const0_rtx; + } + else + operands[8] = gen_highpart (SImode, operands[3]); + operands[9] = gen_lowpart (SImode, operands[3]); +}") (define_insn "*and_not_di_sp32" [(set (match_operand:DI 0 "register_operand" "=r,b") |