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| author | Jim Wilson <wilson@gcc.gnu.org> | 1993-10-05 21:08:07 -0700 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 1993-10-05 21:08:07 -0700 |
| commit | 13a7eb33484fb00e34f119bbd55aed313d5bd09e (patch) | |
| tree | 2895000eec0a61ebb3b5f97f34af0353000ac789 /gcc/config/sparc | |
| parent | 922bd191bc3f3aedad6ba95ac8aa1b88b24c744a (diff) | |
| download | gcc-13a7eb33484fb00e34f119bbd55aed313d5bd09e.zip gcc-13a7eb33484fb00e34f119bbd55aed313d5bd09e.tar.gz gcc-13a7eb33484fb00e34f119bbd55aed313d5bd09e.tar.bz2 | |
(umulsidi3): Use uns_arith_operand not arith_operand.
(const_umulsidi3): Use uns_small_int not small_int.
(ashlsi3+1, ashlsi3+2): New patterns to replace shift
and compare with addcc.
From-SVN: r5628
Diffstat (limited to 'gcc/config/sparc')
| -rw-r--r-- | gcc/config/sparc/sparc.md | 23 |
1 files changed, 21 insertions, 2 deletions
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index dcb96e9..684a435 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -1840,7 +1840,7 @@ (define_expand "umulsidi3" [(set (match_operand:DI 0 "register_operand" "") (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "")) - (zero_extend:DI (match_operand:SI 2 "arith_operand" ""))))] + (zero_extend:DI (match_operand:SI 2 "uns_arith_operand" ""))))] "TARGET_V8 || TARGET_SPARCLITE" " { @@ -1864,7 +1864,7 @@ (define_insn "const_umulsidi3" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) - (match_operand:SI 2 "small_int" "I")))] + (match_operand:SI 2 "uns_small_int" "")))] "TARGET_V8 || TARGET_SPARCLITE" "umul %1,%2,%R0\;rd %%y,%0" [(set_attr "length" "2")]) @@ -2529,6 +2529,25 @@ "" "sll %1,%2,%0") +(define_insn "" + [(set (reg:CC_NOOV 0) + (compare:CC_NOOV (ashift:SI (match_operand:SI 0 "register_operand" "r") + (const_int 1)) + (const_int 0)))] + "" + "addcc %0,%0,%%g0" + [(set_attr "type" "compare")]) + +(define_insn "" + [(set (reg:CC_NOOV 0) + (compare:CC_NOOV (ashift:SI (match_operand:SI 1 "register_operand" "r") + (const_int 1)) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") + (ashift:SI (match_dup 1) (const_int 1)))] + "" + "addcc %1,%1,%0") + (define_insn "ashrsi3" [(set (match_operand:SI 0 "register_operand" "=r") (ashiftrt:SI (match_operand:SI 1 "register_operand" "r") |