Merge from trunk revision 104c05c5284b7822d770ee51a7d91946c7e56d50.

7 files changed, 160 insertions, 174 deletions

diff --git a/gcc/config/sparc/driver-sparc.c b/gcc/config/sparc/driver-sparc.c
index f70c53f..698c18e 100644
--- a/gcc/config/sparc/driver-sparc.c
+++ b/gcc/config/sparc/driver-sparc.c
@@ -148,7 +148,7 @@ host_detect_local_cpu (int argc, const char **argv)
     return NULL;
 
   while (fgets (buf, sizeof (buf), f) != NULL)
-    if (strncmp (buf, "cpu\t\t:", sizeof ("cpu\t\t:") - 1) == 0)
+    if (startswith (buf, "cpu\t\t:"))
       {
         for (i = 0; cpu_names [i].name; i++)
           if (strstr (buf, cpu_names [i].name) != NULL)
diff --git a/gcc/config/sparc/rtemself.h b/gcc/config/sparc/rtemself.h
index fa972af..d64ce90 100644
--- a/gcc/config/sparc/rtemself.h
+++ b/gcc/config/sparc/rtemself.h
@@ -40,3 +40,5 @@
 
 /* Use the default */
 #undef LINK_GCC_C_SEQUENCE_SPEC
+
+#define SPARC_GCOV_TYPE_SIZE 32
diff --git a/gcc/config/sparc/sparc-d.c b/gcc/config/sparc/sparc-d.c
index 186e965..cfb8dae 100644
--- a/gcc/config/sparc/sparc-d.c
+++ b/gcc/config/sparc/sparc-d.c
@@ -15,6 +15,8 @@ You should have received a copy of the GNU General Public License
 along with GCC; see the file COPYING3.  If not see
 <http://www.gnu.org/licenses/>.  */
 
+#define IN_TARGET_CODE 1
+
 #include "config.h"
 #include "system.h"
 #include "coretypes.h"
@@ -46,3 +48,31 @@ sparc_d_target_versions (void)
       d_add_builtin_version ("SPARC_SoftFloat");
     }
 }
+
+/* Handle a call to `__traits(getTargetInfo, "floatAbi")'.  */
+
+static tree
+sparc_d_handle_target_float_abi (void)
+{
+  const char *abi;
+
+  if (TARGET_FPU)
+    abi = "hard";
+  else
+    abi = "soft";
+
+  return build_string_literal (strlen (abi) + 1, abi);
+}
+
+/* Implement TARGET_D_REGISTER_CPU_TARGET_INFO.  */
+
+void
+sparc_d_register_target_info (void)
+{
+  const struct d_target_info_spec handlers[] = {
+    { "floatAbi", sparc_d_handle_target_float_abi },
+    { NULL, NULL },
+  };
+
+  d_add_target_info_handlers (handlers);
+}
diff --git a/gcc/config/sparc/sparc-protos.h b/gcc/config/sparc/sparc-protos.h
index ef94d4f..8879ac3 100644
--- a/gcc/config/sparc/sparc-protos.h
+++ b/gcc/config/sparc/sparc-protos.h
@@ -30,7 +30,8 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree);
 extern unsigned long sparc_type_code (tree);
 #endif /* TREE_CODE */
 
-extern void order_regs_for_local_alloc (void);
+extern void sparc_order_regs_for_local_alloc (void);
+extern int sparc_leaf_reg_remap (int);
 extern int sparc_initial_elimination_offset (int);
 extern void sparc_expand_prologue (void);
 extern void sparc_flat_expand_prologue (void);
@@ -113,5 +114,6 @@ extern rtl_opt_pass *make_pass_work_around_errata (gcc::context *);
 
 /* Routines implemented in sparc-d.c  */
 extern void sparc_d_target_versions (void);
+extern void sparc_d_register_target_info (void);
 
 #endif /* __SPARC_PROTOS_H__ */
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 42ba415..06f41d7 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -507,25 +507,6 @@ static const struct processor_costs *sparc_costs = &cypress_costs;
   ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
 #endif
 
-/* Vector to say how input registers are mapped to output registers.
-   HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
-   eliminate it.  You must use -fomit-frame-pointer to get that.  */
-char leaf_reg_remap[] =
-{ 0, 1, 2, 3, 4, 5, 6, 7,
-  -1, -1, -1, -1, -1, -1, 14, -1,
-  -1, -1, -1, -1, -1, -1, -1, -1,
-  8, 9, 10, 11, 12, 13, -1, 15,
-
-  32, 33, 34, 35, 36, 37, 38, 39,
-  40, 41, 42, 43, 44, 45, 46, 47,
-  48, 49, 50, 51, 52, 53, 54, 55,
-  56, 57, 58, 59, 60, 61, 62, 63,
-  64, 65, 66, 67, 68, 69, 70, 71,
-  72, 73, 74, 75, 76, 77, 78, 79,
-  80, 81, 82, 83, 84, 85, 86, 87,
-  88, 89, 90, 91, 92, 93, 94, 95,
-  96, 97, 98, 99, 100, 101, 102};
-
 /* Vector, indexed by hard register number, which contains 1
    for a register that is allowable in a candidate for leaf
    function treatment.  */
@@ -963,6 +944,17 @@ char sparc_hard_reg_printed[8];
 #undef TARGET_ZERO_CALL_USED_REGS
 #define TARGET_ZERO_CALL_USED_REGS sparc_zero_call_used_regs
 
+#ifdef SPARC_GCOV_TYPE_SIZE
+static HOST_WIDE_INT
+sparc_gcov_type_size (void)
+{
+  return SPARC_GCOV_TYPE_SIZE;
+}
+
+#undef TARGET_GCOV_TYPE_SIZE
+#define TARGET_GCOV_TYPE_SIZE sparc_gcov_type_size
+#endif
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 /* Return the memory reference contained in X if any, zero otherwise.  */
@@ -4213,26 +4205,7 @@ sparc_got (void)
   return got_symbol_rtx;
 }
 
-/* Wrapper around the load_pcrel_sym{si,di} patterns.  */
-
-static rtx
-gen_load_pcrel_sym (rtx op0, rtx op1, rtx op2)
-{
-  int orig_flag_pic = flag_pic;
-  rtx insn;
-
-  /* The load_pcrel_sym{si,di} patterns require absolute addressing.  */
-  flag_pic = 0;
-  if (TARGET_ARCH64)
-    insn = gen_load_pcrel_symdi (op0, op1, op2, GEN_INT (REGNO (op0)));
-  else
-    insn = gen_load_pcrel_symsi (op0, op1, op2, GEN_INT (REGNO (op0)));
-  flag_pic = orig_flag_pic;
-
-  return insn;
-}
-
-/* Output the load_pcrel_sym{si,di} patterns.  */
+/* Output the load_pcrel_sym pattern.  */
 
 const char *
 output_load_pcrel_sym (rtx *operands)
@@ -4299,8 +4272,15 @@ load_got_register (void)
 	  got_helper_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
 	}
 
-      insn
-	= gen_load_pcrel_sym (got_register_rtx, sparc_got (), got_helper_rtx);
+      /* The load_pcrel_sym{si,di} patterns require absolute addressing.  */
+      const int orig_flag_pic = flag_pic;
+      flag_pic = 0;
+      insn = gen_load_pcrel_sym (Pmode,
+				 got_register_rtx,
+				 sparc_got (),
+				 got_helper_rtx,
+				 GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM));
+      flag_pic = orig_flag_pic;
     }
 
   emit_insn (insn);
@@ -4680,22 +4660,11 @@ sparc_legitimize_tls_address (rtx addr)
 	ret = gen_reg_rtx (Pmode);
 	o0 = gen_rtx_REG (Pmode, 8);
 	got = sparc_tls_got ();
-	if (TARGET_ARCH32)
-	  {
-	    emit_insn (gen_tgd_hi22si (temp1, addr));
-	    emit_insn (gen_tgd_lo10si (temp2, temp1, addr));
-	    emit_insn (gen_tgd_addsi (o0, got, temp2, addr));
-	    insn = emit_call_insn (gen_tgd_callsi (o0, sparc_tls_get_addr (),
-						   addr, const1_rtx));
-	  }
-	else
-	  {
-	    emit_insn (gen_tgd_hi22di (temp1, addr));
-	    emit_insn (gen_tgd_lo10di (temp2, temp1, addr));
-	    emit_insn (gen_tgd_adddi (o0, got, temp2, addr));
-	    insn = emit_call_insn (gen_tgd_calldi (o0, sparc_tls_get_addr (),
-						   addr, const1_rtx));
-	  }
+	emit_insn (gen_tgd_hi22 (Pmode, temp1, addr));
+	emit_insn (gen_tgd_lo10 (Pmode, temp2, temp1, addr));
+	emit_insn (gen_tgd_add (Pmode, o0, got, temp2, addr));
+	insn = emit_call_insn (gen_tgd_call (Pmode, o0, sparc_tls_get_addr (),
+					     addr, const1_rtx));
 	use_reg (&CALL_INSN_FUNCTION_USAGE (insn), o0);
 	RTL_CONST_CALL_P (insn) = 1;
 	insn = get_insns ();
@@ -4711,22 +4680,11 @@ sparc_legitimize_tls_address (rtx addr)
 	ret = gen_reg_rtx (Pmode);
 	o0 = gen_rtx_REG (Pmode, 8);
 	got = sparc_tls_got ();
-	if (TARGET_ARCH32)
-	  {
-	    emit_insn (gen_tldm_hi22si (temp1));
-	    emit_insn (gen_tldm_lo10si (temp2, temp1));
-	    emit_insn (gen_tldm_addsi (o0, got, temp2));
-	    insn = emit_call_insn (gen_tldm_callsi (o0, sparc_tls_get_addr (),
-						    const1_rtx));
-	  }
-	else
-	  {
-	    emit_insn (gen_tldm_hi22di (temp1));
-	    emit_insn (gen_tldm_lo10di (temp2, temp1));
-	    emit_insn (gen_tldm_adddi (o0, got, temp2));
-	    insn = emit_call_insn (gen_tldm_calldi (o0, sparc_tls_get_addr (),
-						    const1_rtx));
-	  }
+	emit_insn (gen_tldm_hi22 (Pmode, temp1));
+	emit_insn (gen_tldm_lo10 (Pmode, temp2, temp1));
+	emit_insn (gen_tldm_add (Pmode, o0, got, temp2));
+	insn = emit_call_insn (gen_tldm_call (Pmode, o0, sparc_tls_get_addr (),
+					      const1_rtx));
 	use_reg (&CALL_INSN_FUNCTION_USAGE (insn), o0);
 	RTL_CONST_CALL_P (insn) = 1;
 	insn = get_insns ();
@@ -4738,18 +4696,9 @@ sparc_legitimize_tls_address (rtx addr)
 					    UNSPEC_TLSLD_BASE));
 	temp1 = gen_reg_rtx (Pmode);
 	temp2 = gen_reg_rtx (Pmode);
-	if (TARGET_ARCH32)
-	  {
-	    emit_insn (gen_tldo_hix22si (temp1, addr));
-	    emit_insn (gen_tldo_lox10si (temp2, temp1, addr));
-	    emit_insn (gen_tldo_addsi (ret, temp3, temp2, addr));
-	  }
-	else
-	  {
-	    emit_insn (gen_tldo_hix22di (temp1, addr));
-	    emit_insn (gen_tldo_lox10di (temp2, temp1, addr));
-	    emit_insn (gen_tldo_adddi (ret, temp3, temp2, addr));
-	  }
+	emit_insn (gen_tldo_hix22 (Pmode, temp1, addr));
+	emit_insn (gen_tldo_lox10 (Pmode, temp2, temp1, addr));
+	emit_insn (gen_tldo_add (Pmode, ret, temp3, temp2, addr));
 	break;
 
       case TLS_MODEL_INITIAL_EXEC:
@@ -4757,27 +4706,17 @@ sparc_legitimize_tls_address (rtx addr)
 	temp2 = gen_reg_rtx (Pmode);
 	temp3 = gen_reg_rtx (Pmode);
 	got = sparc_tls_got ();
+	emit_insn (gen_tie_hi22 (Pmode, temp1, addr));
+	emit_insn (gen_tie_lo10 (Pmode, temp2, temp1, addr));
 	if (TARGET_ARCH32)
-	  {
-	    emit_insn (gen_tie_hi22si (temp1, addr));
-	    emit_insn (gen_tie_lo10si (temp2, temp1, addr));
-	    emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
-	  }
+	  emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
 	else
-	  {
-	    emit_insn (gen_tie_hi22di (temp1, addr));
-	    emit_insn (gen_tie_lo10di (temp2, temp1, addr));
-	    emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
-	  }
+	  emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
         if (TARGET_SUN_TLS)
 	  {
 	    ret = gen_reg_rtx (Pmode);
-	    if (TARGET_ARCH32)
-	      emit_insn (gen_tie_addsi (ret, gen_rtx_REG (Pmode, 7),
-					temp3, addr));
-	    else
-	      emit_insn (gen_tie_adddi (ret, gen_rtx_REG (Pmode, 7),
-					temp3, addr));
+	    emit_insn (gen_tie_add (Pmode, ret, gen_rtx_REG (Pmode, 7),
+				    temp3, addr));
 	  }
 	else
 	  ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
@@ -4786,16 +4725,8 @@ sparc_legitimize_tls_address (rtx addr)
       case TLS_MODEL_LOCAL_EXEC:
 	temp1 = gen_reg_rtx (Pmode);
 	temp2 = gen_reg_rtx (Pmode);
-	if (TARGET_ARCH32)
-	  {
-	    emit_insn (gen_tle_hix22si (temp1, addr));
-	    emit_insn (gen_tle_lox10si (temp2, temp1, addr));
-	  }
-	else
-	  {
-	    emit_insn (gen_tle_hix22di (temp1, addr));
-	    emit_insn (gen_tle_lox10di (temp2, temp1, addr));
-	  }
+	emit_insn (gen_tle_hix22 (Pmode, temp1, addr));
+	emit_insn (gen_tle_lox10 (Pmode, temp2, temp1, addr));
 	ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
 	break;
 
@@ -5696,10 +5627,7 @@ sparc_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
 	 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
 	 until it is equal to ROUNDED_SIZE.  */
 
-      if (TARGET_ARCH64)
-	emit_insn (gen_probe_stack_rangedi (g1, g1, g4));
-      else
-	emit_insn (gen_probe_stack_rangesi (g1, g1, g4));
+      emit_insn (gen_probe_stack_range (Pmode, g1, g1, g4));
 
 
       /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
@@ -8873,7 +8801,6 @@ epilogue_renumber (rtx *where, int test)
 	*where = gen_rtx_REG (GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
       /* fallthrough */
     case SCRATCH:
-    case CC0:
     case PC:
     case CONST_INT:
     case CONST_WIDE_INT:
@@ -8928,18 +8855,18 @@ epilogue_renumber (rtx *where, int test)
 
 /* Leaf functions and non-leaf functions have different needs.  */
 
-static const int
-reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
+static const int reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
 
-static const int
-reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
+static const int reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
 
-static const int *const reg_alloc_orders[] = {
+static const int *const reg_alloc_orders[] =
+{
   reg_leaf_alloc_order,
-  reg_nonleaf_alloc_order};
+  reg_nonleaf_alloc_order
+};
 
 void
-order_regs_for_local_alloc (void)
+sparc_order_regs_for_local_alloc (void)
 {
   static int last_order_nonleaf = 1;
 
@@ -8951,7 +8878,28 @@ order_regs_for_local_alloc (void)
 	      FIRST_PSEUDO_REGISTER * sizeof (int));
     }
 }
-
+
+int
+sparc_leaf_reg_remap (int regno)
+{
+  gcc_checking_assert (regno >= 0);
+
+  /* Do not remap in flat mode.  */
+  if (TARGET_FLAT)
+    return regno;
+
+  /* Do not remap global, stack pointer or floating-point registers.  */
+  if (regno < 8 || regno == STACK_POINTER_REGNUM || regno > SPARC_LAST_INT_REG)
+    return regno;
+
+  /* Neither out nor local nor frame pointer registers must appear.  */
+  if ((regno >= 8 && regno <= 23) || regno == HARD_FRAME_POINTER_REGNUM)
+    return -1;
+
+  /* Remap in to out registers.  */
+  return regno - 16;
+}
+
 /* Return 1 if REG and MEM are legitimate enough to allow the various
    MEM<-->REG splits to be run.  */
 
@@ -9940,9 +9888,11 @@ sparc32_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt)
 		   GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
 		   NULL_RTX, 1, OPTAB_DIRECT));
 
+  emit_insn
+    (gen_flush (SImode, validize_mem (adjust_address (m_tramp, SImode, 0))));
+
   /* On UltraSPARC a flush flushes an entire cache line.  The trampoline is
      aligned on a 16 byte boundary so one flush clears it all.  */
-  emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp, SImode, 0))));
   if (sparc_cpu != PROCESSOR_ULTRASPARC
       && sparc_cpu != PROCESSOR_ULTRASPARC3
       && sparc_cpu != PROCESSOR_NIAGARA
@@ -9951,7 +9901,8 @@ sparc32_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt)
       && sparc_cpu != PROCESSOR_NIAGARA4
       && sparc_cpu != PROCESSOR_NIAGARA7
       && sparc_cpu != PROCESSOR_M8)
-    emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp, SImode, 8))));
+    emit_insn
+      (gen_flush (SImode, validize_mem (adjust_address (m_tramp, SImode, 8))));
 
   /* Call __enable_execute_stack after writing onto the stack to make sure
      the stack address is accessible.  */
@@ -9988,8 +9939,11 @@ sparc64_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt)
 		  GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
   emit_move_insn (adjust_address (m_tramp, DImode, 16), cxt);
   emit_move_insn (adjust_address (m_tramp, DImode, 24), fnaddr);
-  emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 0))));
+  emit_insn
+    (gen_flush (DImode, validize_mem (adjust_address (m_tramp, DImode, 0))));
 
+  /* On UltraSPARC a flush flushes an entire cache line.  The trampoline is
+     aligned on a 16 byte boundary so one flush clears it all.  */
   if (sparc_cpu != PROCESSOR_ULTRASPARC
       && sparc_cpu != PROCESSOR_ULTRASPARC3
       && sparc_cpu != PROCESSOR_NIAGARA
@@ -9998,7 +9952,8 @@ sparc64_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt)
       && sparc_cpu != PROCESSOR_NIAGARA4
       && sparc_cpu != PROCESSOR_NIAGARA7
       && sparc_cpu != PROCESSOR_M8)
-    emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 8))));
+    emit_insn
+      (gen_flush (DImode, validize_mem (adjust_address (m_tramp, DImode, 8))));
 
   /* Call __enable_execute_stack after writing onto the stack to make sure
      the stack address is accessible.  */
@@ -13041,14 +12996,11 @@ sparc_conditional_register_usage (void)
     fixed_regs[4] = 1;
   else if (fixed_regs[4] == 2)
     fixed_regs[4] = 0;
+
+  /* Disable leaf function optimization in flat mode.  */
   if (TARGET_FLAT)
-    {
-      int regno;
-      /* Disable leaf functions.  */
-      memset (sparc_leaf_regs, 0, FIRST_PSEUDO_REGISTER);
-      for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
-	leaf_reg_remap [regno] = regno;
-    }
+    memset (sparc_leaf_regs, 0, FIRST_PSEUDO_REGISTER);
+
   if (TARGET_VIS)
     global_regs[SPARC_GSR_REG] = 1;
 }
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index cec2f5a..4da5a06 100644
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -27,8 +27,9 @@ along with GCC; see the file COPYING3.  If not see
 
 #define TARGET_CPU_CPP_BUILTINS() sparc_target_macros ()
 
-/* Target CPU versions for D.  */
+/* Target hooks for D language.  */
 #define TARGET_D_CPU_VERSIONS sparc_d_target_versions
+#define TARGET_D_REGISTER_CPU_TARGET_INFO sparc_d_register_target_info
 
 /* Specify this in a cover file to provide bi-architecture (32/64) support.  */
 /* #define SPARC_BI_ARCH */
@@ -964,13 +965,12 @@ extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
   96, 97, 98, 99,			/* %fcc0-3 */	\
   100, 0, 14, 30, 31, 101, 102 }	/* %icc, %g0, %o6, %i6, %i7, %sfp, %gsr */
 
-#define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc ()
+#define ADJUST_REG_ALLOC_ORDER sparc_order_regs_for_local_alloc ()
 
 extern char sparc_leaf_regs[];
 #define LEAF_REGISTERS sparc_leaf_regs
 
-extern char leaf_reg_remap[];
-#define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
+#define LEAF_REG_REMAP(REGNO) sparc_leaf_reg_remap (REGNO)
 
 /* The class value for index registers, and the one for base regs.  */
 #define INDEX_REG_CLASS GENERAL_REGS
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index c5d3696..24b76e0 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -855,7 +855,7 @@
    (clobber (reg:CCX CC_REG))]
   "TARGET_ARCH64 && TARGET_VIS3"
   "#"
-  ""
+  "&& 1"
   [(set (reg:CCXC CC_REG) (compare:CCXC (not:DI (match_dup 1)) (const_int -1)))
    (set (match_dup 0) (ltu:W (reg:CCXC CC_REG) (const_int 0)))]
   ""
@@ -882,7 +882,7 @@
    (clobber (reg:CCX CC_REG))]
   "TARGET_ARCH64 && TARGET_SUBXC"
   "#"
-  ""
+  "&& 1"
   [(set (reg:CCXC CC_REG) (compare:CCXC (not:DI (match_dup 1)) (const_int -1)))
    (set (match_dup 0) (neg:W (ltu:W (reg:CCXC CC_REG) (const_int 0))))]
   ""
@@ -984,7 +984,7 @@
    (clobber (reg:CCX CC_REG))]
   "TARGET_ARCH64 && TARGET_VIS3"
   "#"
-  ""
+  "&& 1"
   [(set (reg:CCXC CC_REG) (compare:CCXC (not:DI (match_dup 1)) (const_int -1)))
    (set (match_dup 0) (plus:W (ltu:W (reg:CCXC CC_REG) (const_int 0))
 			      (match_dup 2)))]
@@ -1000,7 +1000,7 @@
    (clobber (reg:CCX CC_REG))]
   "TARGET_ARCH64 && TARGET_VIS3"
   "#"
-  ""
+  "&& 1"
   [(set (reg:CCXC CC_REG) (compare:CCXC (not:DI (match_dup 1)) (const_int -1)))
    (set (match_dup 0) (plus:W (plus:W (ltu:W (reg:CCXC CC_REG) (const_int 0))
 				      (match_dup 2))
@@ -1048,7 +1048,7 @@
    (clobber (reg:CCX CC_REG))]
   "TARGET_ARCH64 && TARGET_SUBXC"
   "#"
-  ""
+  "&& 1"
   [(set (reg:CCXC CC_REG) (compare:CCXC (not:DI (match_dup 1)) (const_int -1)))
    (set (match_dup 0) (minus:W (match_dup 2)
 			       (ltu:W (reg:CCXC CC_REG) (const_int 0))))]
@@ -1064,7 +1064,7 @@
    (clobber (reg:CCX CC_REG))]
   "TARGET_ARCH64 && TARGET_SUBXC"
   "#"
-  ""
+  "&& 1"
   [(set (reg:CCXC CC_REG) (compare:CCXC (not:DI (match_dup 1)) (const_int -1)))
    (set (match_dup 0) (minus:W (minus:W (match_dup 2)
 				        (ltu:W (reg:CCXC CC_REG) (const_int 0)))
@@ -1592,7 +1592,7 @@
 ;; because the RDPC instruction is extremely expensive and incurs a complete
 ;; instruction pipeline flush.
 
-(define_insn "load_pcrel_sym<P:mode>"
+(define_insn "@load_pcrel_sym<P:mode>"
   [(set (match_operand:P 0 "register_operand" "=r")
 	(unspec:P [(match_operand:P 1 "symbolic_operand" "")
 		   (match_operand:P 2 "call_address_operand" "")
@@ -7290,7 +7290,7 @@ visl")
     = adjust_address (operands[0], GET_MODE (operands[0]), SPARC_STACK_BIAS);
 })
 
-(define_insn "probe_stack_range<P:mode>"
+(define_insn "@probe_stack_range<P:mode>"
   [(set (match_operand:P 0 "register_operand" "=r")
 	(unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
 			    (match_operand:P 2 "register_operand" "r")]
@@ -7468,7 +7468,7 @@ visl")
 
 ;; Special pattern for the FLUSH instruction.
 
-(define_insn "flush<P:mode>"
+(define_insn "@flush<P:mode>"
   [(unspec_volatile [(match_operand:P 0 "memory_operand" "m")] UNSPECV_FLUSH)]
   ""
 {
@@ -7935,14 +7935,14 @@ visl")
 
 ;; TLS support instructions.
 
-(define_insn "tgd_hi22<P:mode>"
+(define_insn "@tgd_hi22<P:mode>"
   [(set (match_operand:P 0 "register_operand" "=r")
         (high:P (unspec:P [(match_operand 1 "tgd_symbolic_operand" "")]
 			  UNSPEC_TLSGD)))]
   "TARGET_TLS"
   "sethi\\t%%tgd_hi22(%a1), %0")
 
-(define_insn "tgd_lo10<P:mode>"
+(define_insn "@tgd_lo10<P:mode>"
   [(set (match_operand:P 0 "register_operand" "=r")
 	(lo_sum:P (match_operand:P 1 "register_operand" "r")
 		  (unspec:P [(match_operand 2 "tgd_symbolic_operand" "")]
@@ -7950,7 +7950,7 @@ visl")
   "TARGET_TLS"
   "add\\t%1, %%tgd_lo10(%a2), %0")
 
-(define_insn "tgd_add<P:mode>"
+(define_insn "@tgd_add<P:mode>"
   [(set (match_operand:P 0 "register_operand" "=r")
 	(plus:P (match_operand:P 1 "register_operand" "r")
 		(unspec:P [(match_operand:P 2 "register_operand" "r")
@@ -7959,7 +7959,7 @@ visl")
   "TARGET_TLS"
   "add\\t%1, %2, %0, %%tgd_add(%a3)")
 
-(define_insn "tgd_call<P:mode>"
+(define_insn "@tgd_call<P:mode>"
   [(set (match_operand 0 "register_operand" "=r")
 	(call (mem:P (unspec:P [(match_operand:P 1 "symbolic_operand" "s")
 				(match_operand 2 "tgd_symbolic_operand" "")]
@@ -7972,20 +7972,20 @@ visl")
                                     (const_string "call")
                                     (const_string "call_no_delay_slot")))])
 
-(define_insn "tldm_hi22<P:mode>"
+(define_insn "@tldm_hi22<P:mode>"
   [(set (match_operand:P 0 "register_operand" "=r")
         (high:P (unspec:P [(const_int 0)] UNSPEC_TLSLDM)))]
   "TARGET_TLS"
   "sethi\\t%%tldm_hi22(%&), %0")
 
-(define_insn "tldm_lo10<P:mode>"
+(define_insn "@tldm_lo10<P:mode>"
   [(set (match_operand:P 0 "register_operand" "=r")
 	(lo_sum:P (match_operand:P 1 "register_operand" "r")
 		  (unspec:P [(const_int 0)] UNSPEC_TLSLDM)))]
   "TARGET_TLS"
   "add\\t%1, %%tldm_lo10(%&), %0")
 
-(define_insn "tldm_add<P:mode>"
+(define_insn "@tldm_add<P:mode>"
   [(set (match_operand:P 0 "register_operand" "=r")
 	(plus:P (match_operand:P 1 "register_operand" "r")
 		(unspec:P [(match_operand:P 2 "register_operand" "r")]
@@ -7993,7 +7993,7 @@ visl")
   "TARGET_TLS"
   "add\\t%1, %2, %0, %%tldm_add(%&)")
 
-(define_insn "tldm_call<P:mode>"
+(define_insn "@tldm_call<P:mode>"
   [(set (match_operand 0 "register_operand" "=r")
 	(call (mem:P (unspec:P [(match_operand:P 1 "symbolic_operand" "s")]
 			       UNSPEC_TLSLDM))
@@ -8005,14 +8005,14 @@ visl")
                                     (const_string "call")
                                     (const_string "call_no_delay_slot")))])
 
-(define_insn "tldo_hix22<P:mode>"
+(define_insn "@tldo_hix22<P:mode>"
   [(set (match_operand:P 0 "register_operand" "=r")
         (high:P (unspec:P [(match_operand 1 "tld_symbolic_operand" "")]
 			  UNSPEC_TLSLDO)))]
   "TARGET_TLS"
   "sethi\\t%%tldo_hix22(%a1), %0")
 
-(define_insn "tldo_lox10<P:mode>"
+(define_insn "@tldo_lox10<P:mode>"
   [(set (match_operand:P 0 "register_operand" "=r")
 	(lo_sum:P (match_operand:P 1 "register_operand" "r")
 		  (unspec:P [(match_operand 2 "tld_symbolic_operand" "")]
@@ -8020,7 +8020,7 @@ visl")
   "TARGET_TLS"
   "xor\\t%1, %%tldo_lox10(%a2), %0")
 
-(define_insn "tldo_add<P:mode>"
+(define_insn "@tldo_add<P:mode>"
   [(set (match_operand:P 0 "register_operand" "=r")
 	(plus:P (match_operand:P 1 "register_operand" "r")
 		(unspec:P [(match_operand:P 2 "register_operand" "r")
@@ -8029,14 +8029,14 @@ visl")
   "TARGET_TLS"
   "add\\t%1, %2, %0, %%tldo_add(%a3)")
 
-(define_insn "tie_hi22<P:mode>"
+(define_insn "@tie_hi22<P:mode>"
   [(set (match_operand:P 0 "register_operand" "=r")
         (high:P (unspec:P [(match_operand 1 "tie_symbolic_operand" "")]
 			  UNSPEC_TLSIE)))]
   "TARGET_TLS"
   "sethi\\t%%tie_hi22(%a1), %0")
 
-(define_insn "tie_lo10<P:mode>"
+(define_insn "@tie_lo10<P:mode>"
   [(set (match_operand:P 0 "register_operand" "=r")
 	(lo_sum:P (match_operand:P 1 "register_operand" "r")
 		  (unspec:P [(match_operand 2 "tie_symbolic_operand" "")]
@@ -8068,7 +8068,7 @@ visl")
   [(set_attr "type" "load")
    (set_attr "subtype" "regular")])
 
-(define_insn "tie_add<P:mode>"
+(define_insn "@tie_add<P:mode>"
   [(set (match_operand:P 0 "register_operand" "=r")
 	(plus:P (match_operand:P 1 "register_operand" "r")
 		(unspec:P [(match_operand:P 2 "register_operand" "r")
@@ -8077,14 +8077,14 @@ visl")
   "TARGET_SUN_TLS"
   "add\\t%1, %2, %0, %%tie_add(%a3)")
 
-(define_insn "tle_hix22<P:mode>"
+(define_insn "@tle_hix22<P:mode>"
   [(set (match_operand:P 0 "register_operand" "=r")
         (high:P (unspec:P [(match_operand 1 "tle_symbolic_operand" "")]
 			  UNSPEC_TLSLE)))]
   "TARGET_TLS"
   "sethi\\t%%tle_hix22(%a1), %0")
 
-(define_insn "tle_lox10<P:mode>"
+(define_insn "@tle_lox10<P:mode>"
   [(set (match_operand:P 0 "register_operand" "=r")
 	(lo_sum:P (match_operand:P 1 "register_operand" "r")
 		  (unspec:P [(match_operand 2 "tle_symbolic_operand" "")]
@@ -8342,13 +8342,13 @@ visl")
   operands[1] = gen_rtx_MEM (Pmode, addr);
 #endif
   if (TARGET_ARCH64)
-    emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
+    emit_insn (gen_stack_protect_set64 (operands[0], operands[1]));
   else
-    emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
+    emit_insn (gen_stack_protect_set32 (operands[0], operands[1]));
   DONE;
 })
 
-(define_insn "stack_protect_setsi"
+(define_insn "stack_protect_set32"
   [(set (match_operand:SI 0 "memory_operand" "=m")
 	(unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
    (set (match_scratch:SI 2 "=&r") (const_int 0))]
@@ -8357,7 +8357,7 @@ visl")
   [(set_attr "type" "multi")
    (set_attr "length" "3")])
 
-(define_insn "stack_protect_setdi"
+(define_insn "stack_protect_set64"
   [(set (match_operand:DI 0 "memory_operand" "=m")
 	(unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
    (set (match_scratch:DI 2 "=&r") (const_int 0))]
@@ -8381,13 +8381,13 @@ visl")
   if (TARGET_ARCH64)
     {
       result = gen_reg_rtx (Pmode);
-      emit_insn (gen_stack_protect_testdi (result, operands[0], operands[1]));
+      emit_insn (gen_stack_protect_test64 (result, operands[0], operands[1]));
       test = gen_rtx_EQ (VOIDmode, result, const0_rtx);
       emit_jump_insn (gen_cbranchdi4 (test, result, const0_rtx, operands[2]));
     }
   else
     {
-      emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
+      emit_insn (gen_stack_protect_test32 (operands[0], operands[1]));
       result = gen_rtx_REG (CCmode, SPARC_ICC_REG);
       test = gen_rtx_EQ (VOIDmode, result, const0_rtx);
       emit_jump_insn (gen_cbranchcc4 (test, result, const0_rtx, operands[2]));
@@ -8395,7 +8395,7 @@ visl")
   DONE;
 })
 
-(define_insn "stack_protect_testsi"
+(define_insn "stack_protect_test32"
   [(set (reg:CC CC_REG)
 	(unspec:CC [(match_operand:SI 0 "memory_operand" "m")
 		    (match_operand:SI 1 "memory_operand" "m")]
@@ -8407,7 +8407,7 @@ visl")
   [(set_attr "type" "multi")
    (set_attr "length" "4")])
 
-(define_insn "stack_protect_testdi"
+(define_insn "stack_protect_test64"
   [(set (match_operand:DI 0 "register_operand" "=&r")
 	(unspec:DI [(match_operand:DI 1 "memory_operand" "m")
 		    (match_operand:DI 2 "memory_operand" "m")]