From 433b6b12dfa5ef109a5d8d40e7b3695dcb749e58 Mon Sep 17 00:00:00 2001 From: Iain Buclaw Date: Fri, 26 Mar 2021 13:12:59 +0100 Subject: d: Define IN_TARGET_CODE in all machine-specific D language files. This is to be consistent with the rest of the back-end. gcc/ChangeLog: * config/aarch64/aarch64-d.c (IN_TARGET_CODE): Define. * config/arm/arm-d.c (IN_TARGET_CODE): Likewise. * config/i386/i386-d.c (IN_TARGET_CODE): Likewise. * config/mips/mips-d.c (IN_TARGET_CODE): Likewise. * config/pa/pa-d.c (IN_TARGET_CODE): Likewise. * config/riscv/riscv-d.c (IN_TARGET_CODE): Likewise. * config/rs6000/rs6000-d.c (IN_TARGET_CODE): Likewise. * config/s390/s390-d.c (IN_TARGET_CODE): Likewise. * config/sparc/sparc-d.c (IN_TARGET_CODE): Likewise. --- gcc/config/sparc/sparc-d.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'gcc/config/sparc') diff --git a/gcc/config/sparc/sparc-d.c b/gcc/config/sparc/sparc-d.c index 186e965..0eb663b 100644 --- a/gcc/config/sparc/sparc-d.c +++ b/gcc/config/sparc/sparc-d.c @@ -15,6 +15,8 @@ You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see . */ +#define IN_TARGET_CODE 1 + #include "config.h" #include "system.h" #include "coretypes.h" -- cgit v1.1 From 3785d2b207f1958f31a79fbbb5705b261551950d Mon Sep 17 00:00:00 2001 From: Iain Buclaw Date: Mon, 5 Apr 2021 19:37:31 +0200 Subject: d: Add TARGET_D_REGISTER_CPU_TARGET_INFO This implements `__traits(getTargetInfo, "floatAbi")' for all targets that have D support files. gcc/ChangeLog: * config/aarch64/aarch64-d.c (aarch64_d_handle_target_float_abi): New function. (aarch64_d_register_target_info): New function. * config/aarch64/aarch64-protos.h (aarch64_d_register_target_info): Declare. * config/aarch64/aarch64.h (TARGET_D_REGISTER_CPU_TARGET_INFO): Define. * config/arm/arm-d.c (arm_d_handle_target_float_abi): New function. (arm_d_register_target_info): New function. * config/arm/arm-protos.h (arm_d_register_target_info): Declare. * config/arm/arm.h (TARGET_D_REGISTER_CPU_TARGET_INFO): Define. * config/i386/i386-d.c (ix86_d_handle_target_float_abi): New function. (ix86_d_register_target_info): New function. * config/i386/i386-protos.h (ix86_d_register_target_info): Declare. * config/i386/i386.h (TARGET_D_REGISTER_CPU_TARGET_INFO): Define. * config/mips/mips-d.c (mips_d_handle_target_float_abi): New function. (mips_d_register_target_info): New function. * config/mips/mips-protos.h (mips_d_register_target_info): Declare. * config/mips/mips.h (TARGET_D_REGISTER_CPU_TARGET_INFO): Define. * config/pa/pa-d.c (pa_d_handle_target_float_abi): New function. (pa_d_register_target_info): New function. * config/pa/pa-protos.h (pa_d_register_target_info): Declare. * config/pa/pa.h (TARGET_D_REGISTER_CPU_TARGET_INFO): Define. * config/riscv/riscv-d.c (riscv_d_handle_target_float_abi): New function. (riscv_d_register_target_info): New function. * config/riscv/riscv-protos.h (riscv_d_register_target_info): Declare. * config/riscv/riscv.h (TARGET_D_REGISTER_CPU_TARGET_INFO): Define. * config/rs6000/rs6000-d.c (rs6000_d_handle_target_float_abi): New function. (rs6000_d_register_target_info): New function. * config/rs6000/rs6000-protos.h (rs6000_d_register_target_info): Declare. * config/rs6000/rs6000.h (TARGET_D_REGISTER_CPU_TARGET_INFO): Define. * config/s390/s390-d.c (s390_d_handle_target_float_abi): New function. (s390_d_register_target_info): New function. * config/s390/s390-protos.h (s390_d_register_target_info): Declare. * config/s390/s390.h (TARGET_D_REGISTER_CPU_TARGET_INFO): Define. * config/sparc/sparc-d.c (sparc_d_handle_target_float_abi): New function. (sparc_d_register_target_info): New function. * config/sparc/sparc-protos.h (sparc_d_register_target_info): Declare. * config/sparc/sparc.h (TARGET_D_REGISTER_CPU_TARGET_INFO): Define. * doc/tm.texi: Regenerate. * doc/tm.texi.in (D language and ABI): Add @hook for TARGET_D_REGISTER_CPU_TARGET_INFO. gcc/d/ChangeLog: * d-target.cc (Target::_init): Call new targetdm hook to register CPU specific target info keys. * d-target.def (d_register_cpu_target_info): New hook. --- gcc/config/sparc/sparc-d.c | 28 ++++++++++++++++++++++++++++ gcc/config/sparc/sparc-protos.h | 1 + gcc/config/sparc/sparc.h | 3 ++- 3 files changed, 31 insertions(+), 1 deletion(-) (limited to 'gcc/config/sparc') diff --git a/gcc/config/sparc/sparc-d.c b/gcc/config/sparc/sparc-d.c index 0eb663b..cfb8dae 100644 --- a/gcc/config/sparc/sparc-d.c +++ b/gcc/config/sparc/sparc-d.c @@ -48,3 +48,31 @@ sparc_d_target_versions (void) d_add_builtin_version ("SPARC_SoftFloat"); } } + +/* Handle a call to `__traits(getTargetInfo, "floatAbi")'. */ + +static tree +sparc_d_handle_target_float_abi (void) +{ + const char *abi; + + if (TARGET_FPU) + abi = "hard"; + else + abi = "soft"; + + return build_string_literal (strlen (abi) + 1, abi); +} + +/* Implement TARGET_D_REGISTER_CPU_TARGET_INFO. */ + +void +sparc_d_register_target_info (void) +{ + const struct d_target_info_spec handlers[] = { + { "floatAbi", sparc_d_handle_target_float_abi }, + { NULL, NULL }, + }; + + d_add_target_info_handlers (handlers); +} diff --git a/gcc/config/sparc/sparc-protos.h b/gcc/config/sparc/sparc-protos.h index ef94d4f..ad875cc 100644 --- a/gcc/config/sparc/sparc-protos.h +++ b/gcc/config/sparc/sparc-protos.h @@ -113,5 +113,6 @@ extern rtl_opt_pass *make_pass_work_around_errata (gcc::context *); /* Routines implemented in sparc-d.c */ extern void sparc_d_target_versions (void); +extern void sparc_d_register_target_info (void); #endif /* __SPARC_PROTOS_H__ */ diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index cec2f5a..4834575 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -27,8 +27,9 @@ along with GCC; see the file COPYING3. If not see #define TARGET_CPU_CPP_BUILTINS() sparc_target_macros () -/* Target CPU versions for D. */ +/* Target hooks for D language. */ #define TARGET_D_CPU_VERSIONS sparc_d_target_versions +#define TARGET_D_REGISTER_CPU_TARGET_INFO sparc_d_register_target_info /* Specify this in a cover file to provide bi-architecture (32/64) support. */ /* #define SPARC_BI_ARCH */ -- cgit v1.1 From 7d6f7aa409ebe37ea9eac25cc131f4a8f03acfa3 Mon Sep 17 00:00:00 2001 From: Eric Botcazou Date: Thu, 29 Apr 2021 13:34:27 +0200 Subject: Small housekeeping work in SPARC back-end gcc/ * config/sparc/sparc.c (gen_load_pcrel_sym): Delete. (load_got_register): Do the PIC dance here. (sparc_legitimize_tls_address): Simplify. (sparc_emit_probe_stack_range): Likewise. (sparc32_initialize_trampoline): Likewise. (sparc64_initialize_trampoline): Likewise. * config/sparc/sparc.md (load_pcrel_sym): Add @ marker. (probe_stack_range): Likewise. (flush): Likewise. (tgd_hi22): Likewise. (tgd_lo10): Likewise. (tgd_add): Likewise. (tgd_call): Likewise. (tldm_hi22): Likewise. (tldm_lo10): Likewise. (tldm_add): Likewise. (tldm_call): Likewise. (tldo_hix22): Likewise. (tldo_lox10): Likewise. (tldo_add): Likewise. (tie_hi22): Likewise. (tie_lo10): Likewise. (tie_add): Likewise. (tle_hix22): Likewise. (tle_lox10): Likewise. (stack_protect_setsi): Rename to... (stack_protect_set32): ...this. (stack_protect_setdi): Rename to... (stack_protect_set64): ...this. (stack_protect_set): Adjust calls to above. (stack_protect_testsi): Rename to... (stack_protect_test32): ...this. (stack_protect_testdi): Rename to... (stack_protect_test64): ...this. (stack_protect_test): Adjust calls to above. --- gcc/config/sparc/sparc.c | 143 ++++++++++++++-------------------------------- gcc/config/sparc/sparc.md | 54 ++++++++--------- 2 files changed, 70 insertions(+), 127 deletions(-) (limited to 'gcc/config/sparc') diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 42ba415..3b4d416 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -4213,26 +4213,7 @@ sparc_got (void) return got_symbol_rtx; } -/* Wrapper around the load_pcrel_sym{si,di} patterns. */ - -static rtx -gen_load_pcrel_sym (rtx op0, rtx op1, rtx op2) -{ - int orig_flag_pic = flag_pic; - rtx insn; - - /* The load_pcrel_sym{si,di} patterns require absolute addressing. */ - flag_pic = 0; - if (TARGET_ARCH64) - insn = gen_load_pcrel_symdi (op0, op1, op2, GEN_INT (REGNO (op0))); - else - insn = gen_load_pcrel_symsi (op0, op1, op2, GEN_INT (REGNO (op0))); - flag_pic = orig_flag_pic; - - return insn; -} - -/* Output the load_pcrel_sym{si,di} patterns. */ +/* Output the load_pcrel_sym pattern. */ const char * output_load_pcrel_sym (rtx *operands) @@ -4299,8 +4280,15 @@ load_got_register (void) got_helper_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name)); } - insn - = gen_load_pcrel_sym (got_register_rtx, sparc_got (), got_helper_rtx); + /* The load_pcrel_sym{si,di} patterns require absolute addressing. */ + const int orig_flag_pic = flag_pic; + flag_pic = 0; + insn = gen_load_pcrel_sym (Pmode, + got_register_rtx, + sparc_got (), + got_helper_rtx, + GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM)); + flag_pic = orig_flag_pic; } emit_insn (insn); @@ -4680,22 +4668,11 @@ sparc_legitimize_tls_address (rtx addr) ret = gen_reg_rtx (Pmode); o0 = gen_rtx_REG (Pmode, 8); got = sparc_tls_got (); - if (TARGET_ARCH32) - { - emit_insn (gen_tgd_hi22si (temp1, addr)); - emit_insn (gen_tgd_lo10si (temp2, temp1, addr)); - emit_insn (gen_tgd_addsi (o0, got, temp2, addr)); - insn = emit_call_insn (gen_tgd_callsi (o0, sparc_tls_get_addr (), - addr, const1_rtx)); - } - else - { - emit_insn (gen_tgd_hi22di (temp1, addr)); - emit_insn (gen_tgd_lo10di (temp2, temp1, addr)); - emit_insn (gen_tgd_adddi (o0, got, temp2, addr)); - insn = emit_call_insn (gen_tgd_calldi (o0, sparc_tls_get_addr (), - addr, const1_rtx)); - } + emit_insn (gen_tgd_hi22 (Pmode, temp1, addr)); + emit_insn (gen_tgd_lo10 (Pmode, temp2, temp1, addr)); + emit_insn (gen_tgd_add (Pmode, o0, got, temp2, addr)); + insn = emit_call_insn (gen_tgd_call (Pmode, o0, sparc_tls_get_addr (), + addr, const1_rtx)); use_reg (&CALL_INSN_FUNCTION_USAGE (insn), o0); RTL_CONST_CALL_P (insn) = 1; insn = get_insns (); @@ -4711,22 +4688,11 @@ sparc_legitimize_tls_address (rtx addr) ret = gen_reg_rtx (Pmode); o0 = gen_rtx_REG (Pmode, 8); got = sparc_tls_got (); - if (TARGET_ARCH32) - { - emit_insn (gen_tldm_hi22si (temp1)); - emit_insn (gen_tldm_lo10si (temp2, temp1)); - emit_insn (gen_tldm_addsi (o0, got, temp2)); - insn = emit_call_insn (gen_tldm_callsi (o0, sparc_tls_get_addr (), - const1_rtx)); - } - else - { - emit_insn (gen_tldm_hi22di (temp1)); - emit_insn (gen_tldm_lo10di (temp2, temp1)); - emit_insn (gen_tldm_adddi (o0, got, temp2)); - insn = emit_call_insn (gen_tldm_calldi (o0, sparc_tls_get_addr (), - const1_rtx)); - } + emit_insn (gen_tldm_hi22 (Pmode, temp1)); + emit_insn (gen_tldm_lo10 (Pmode, temp2, temp1)); + emit_insn (gen_tldm_add (Pmode, o0, got, temp2)); + insn = emit_call_insn (gen_tldm_call (Pmode, o0, sparc_tls_get_addr (), + const1_rtx)); use_reg (&CALL_INSN_FUNCTION_USAGE (insn), o0); RTL_CONST_CALL_P (insn) = 1; insn = get_insns (); @@ -4738,18 +4704,9 @@ sparc_legitimize_tls_address (rtx addr) UNSPEC_TLSLD_BASE)); temp1 = gen_reg_rtx (Pmode); temp2 = gen_reg_rtx (Pmode); - if (TARGET_ARCH32) - { - emit_insn (gen_tldo_hix22si (temp1, addr)); - emit_insn (gen_tldo_lox10si (temp2, temp1, addr)); - emit_insn (gen_tldo_addsi (ret, temp3, temp2, addr)); - } - else - { - emit_insn (gen_tldo_hix22di (temp1, addr)); - emit_insn (gen_tldo_lox10di (temp2, temp1, addr)); - emit_insn (gen_tldo_adddi (ret, temp3, temp2, addr)); - } + emit_insn (gen_tldo_hix22 (Pmode, temp1, addr)); + emit_insn (gen_tldo_lox10 (Pmode, temp2, temp1, addr)); + emit_insn (gen_tldo_add (Pmode, ret, temp3, temp2, addr)); break; case TLS_MODEL_INITIAL_EXEC: @@ -4757,27 +4714,17 @@ sparc_legitimize_tls_address (rtx addr) temp2 = gen_reg_rtx (Pmode); temp3 = gen_reg_rtx (Pmode); got = sparc_tls_got (); + emit_insn (gen_tie_hi22 (Pmode, temp1, addr)); + emit_insn (gen_tie_lo10 (Pmode, temp2, temp1, addr)); if (TARGET_ARCH32) - { - emit_insn (gen_tie_hi22si (temp1, addr)); - emit_insn (gen_tie_lo10si (temp2, temp1, addr)); - emit_insn (gen_tie_ld32 (temp3, got, temp2, addr)); - } + emit_insn (gen_tie_ld32 (temp3, got, temp2, addr)); else - { - emit_insn (gen_tie_hi22di (temp1, addr)); - emit_insn (gen_tie_lo10di (temp2, temp1, addr)); - emit_insn (gen_tie_ld64 (temp3, got, temp2, addr)); - } + emit_insn (gen_tie_ld64 (temp3, got, temp2, addr)); if (TARGET_SUN_TLS) { ret = gen_reg_rtx (Pmode); - if (TARGET_ARCH32) - emit_insn (gen_tie_addsi (ret, gen_rtx_REG (Pmode, 7), - temp3, addr)); - else - emit_insn (gen_tie_adddi (ret, gen_rtx_REG (Pmode, 7), - temp3, addr)); + emit_insn (gen_tie_add (Pmode, ret, gen_rtx_REG (Pmode, 7), + temp3, addr)); } else ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3); @@ -4786,16 +4733,8 @@ sparc_legitimize_tls_address (rtx addr) case TLS_MODEL_LOCAL_EXEC: temp1 = gen_reg_rtx (Pmode); temp2 = gen_reg_rtx (Pmode); - if (TARGET_ARCH32) - { - emit_insn (gen_tle_hix22si (temp1, addr)); - emit_insn (gen_tle_lox10si (temp2, temp1, addr)); - } - else - { - emit_insn (gen_tle_hix22di (temp1, addr)); - emit_insn (gen_tle_lox10di (temp2, temp1, addr)); - } + emit_insn (gen_tle_hix22 (Pmode, temp1, addr)); + emit_insn (gen_tle_lox10 (Pmode, temp2, temp1, addr)); ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2); break; @@ -5696,10 +5635,7 @@ sparc_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size) probes at FIRST + N * PROBE_INTERVAL for values of N from 1 until it is equal to ROUNDED_SIZE. */ - if (TARGET_ARCH64) - emit_insn (gen_probe_stack_rangedi (g1, g1, g4)); - else - emit_insn (gen_probe_stack_rangesi (g1, g1, g4)); + emit_insn (gen_probe_stack_range (Pmode, g1, g1, g4)); /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time @@ -9940,9 +9876,11 @@ sparc32_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt) GEN_INT (trunc_int_for_mode (0x8410a000, SImode)), NULL_RTX, 1, OPTAB_DIRECT)); + emit_insn + (gen_flush (SImode, validize_mem (adjust_address (m_tramp, SImode, 0)))); + /* On UltraSPARC a flush flushes an entire cache line. The trampoline is aligned on a 16 byte boundary so one flush clears it all. */ - emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp, SImode, 0)))); if (sparc_cpu != PROCESSOR_ULTRASPARC && sparc_cpu != PROCESSOR_ULTRASPARC3 && sparc_cpu != PROCESSOR_NIAGARA @@ -9951,7 +9889,8 @@ sparc32_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt) && sparc_cpu != PROCESSOR_NIAGARA4 && sparc_cpu != PROCESSOR_NIAGARA7 && sparc_cpu != PROCESSOR_M8) - emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp, SImode, 8)))); + emit_insn + (gen_flush (SImode, validize_mem (adjust_address (m_tramp, SImode, 8)))); /* Call __enable_execute_stack after writing onto the stack to make sure the stack address is accessible. */ @@ -9988,8 +9927,11 @@ sparc64_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt) GEN_INT (trunc_int_for_mode (0xca586010, SImode))); emit_move_insn (adjust_address (m_tramp, DImode, 16), cxt); emit_move_insn (adjust_address (m_tramp, DImode, 24), fnaddr); - emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 0)))); + emit_insn + (gen_flush (DImode, validize_mem (adjust_address (m_tramp, DImode, 0)))); + /* On UltraSPARC a flush flushes an entire cache line. The trampoline is + aligned on a 16 byte boundary so one flush clears it all. */ if (sparc_cpu != PROCESSOR_ULTRASPARC && sparc_cpu != PROCESSOR_ULTRASPARC3 && sparc_cpu != PROCESSOR_NIAGARA @@ -9998,7 +9940,8 @@ sparc64_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt) && sparc_cpu != PROCESSOR_NIAGARA4 && sparc_cpu != PROCESSOR_NIAGARA7 && sparc_cpu != PROCESSOR_M8) - emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 8)))); + emit_insn + (gen_flush (DImode, validize_mem (adjust_address (m_tramp, DImode, 8)))); /* Call __enable_execute_stack after writing onto the stack to make sure the stack address is accessible. */ diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index c5d3696..a8d9962 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -1592,7 +1592,7 @@ ;; because the RDPC instruction is extremely expensive and incurs a complete ;; instruction pipeline flush. -(define_insn "load_pcrel_sym" +(define_insn "@load_pcrel_sym" [(set (match_operand:P 0 "register_operand" "=r") (unspec:P [(match_operand:P 1 "symbolic_operand" "") (match_operand:P 2 "call_address_operand" "") @@ -7290,7 +7290,7 @@ visl") = adjust_address (operands[0], GET_MODE (operands[0]), SPARC_STACK_BIAS); }) -(define_insn "probe_stack_range" +(define_insn "@probe_stack_range" [(set (match_operand:P 0 "register_operand" "=r") (unspec_volatile:P [(match_operand:P 1 "register_operand" "0") (match_operand:P 2 "register_operand" "r")] @@ -7468,7 +7468,7 @@ visl") ;; Special pattern for the FLUSH instruction. -(define_insn "flush" +(define_insn "@flush" [(unspec_volatile [(match_operand:P 0 "memory_operand" "m")] UNSPECV_FLUSH)] "" { @@ -7935,14 +7935,14 @@ visl") ;; TLS support instructions. -(define_insn "tgd_hi22" +(define_insn "@tgd_hi22" [(set (match_operand:P 0 "register_operand" "=r") (high:P (unspec:P [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD)))] "TARGET_TLS" "sethi\\t%%tgd_hi22(%a1), %0") -(define_insn "tgd_lo10" +(define_insn "@tgd_lo10" [(set (match_operand:P 0 "register_operand" "=r") (lo_sum:P (match_operand:P 1 "register_operand" "r") (unspec:P [(match_operand 2 "tgd_symbolic_operand" "")] @@ -7950,7 +7950,7 @@ visl") "TARGET_TLS" "add\\t%1, %%tgd_lo10(%a2), %0") -(define_insn "tgd_add" +(define_insn "@tgd_add" [(set (match_operand:P 0 "register_operand" "=r") (plus:P (match_operand:P 1 "register_operand" "r") (unspec:P [(match_operand:P 2 "register_operand" "r") @@ -7959,7 +7959,7 @@ visl") "TARGET_TLS" "add\\t%1, %2, %0, %%tgd_add(%a3)") -(define_insn "tgd_call" +(define_insn "@tgd_call" [(set (match_operand 0 "register_operand" "=r") (call (mem:P (unspec:P [(match_operand:P 1 "symbolic_operand" "s") (match_operand 2 "tgd_symbolic_operand" "")] @@ -7972,20 +7972,20 @@ visl") (const_string "call") (const_string "call_no_delay_slot")))]) -(define_insn "tldm_hi22" +(define_insn "@tldm_hi22" [(set (match_operand:P 0 "register_operand" "=r") (high:P (unspec:P [(const_int 0)] UNSPEC_TLSLDM)))] "TARGET_TLS" "sethi\\t%%tldm_hi22(%&), %0") -(define_insn "tldm_lo10" +(define_insn "@tldm_lo10" [(set (match_operand:P 0 "register_operand" "=r") (lo_sum:P (match_operand:P 1 "register_operand" "r") (unspec:P [(const_int 0)] UNSPEC_TLSLDM)))] "TARGET_TLS" "add\\t%1, %%tldm_lo10(%&), %0") -(define_insn "tldm_add" +(define_insn "@tldm_add" [(set (match_operand:P 0 "register_operand" "=r") (plus:P (match_operand:P 1 "register_operand" "r") (unspec:P [(match_operand:P 2 "register_operand" "r")] @@ -7993,7 +7993,7 @@ visl") "TARGET_TLS" "add\\t%1, %2, %0, %%tldm_add(%&)") -(define_insn "tldm_call" +(define_insn "@tldm_call" [(set (match_operand 0 "register_operand" "=r") (call (mem:P (unspec:P [(match_operand:P 1 "symbolic_operand" "s")] UNSPEC_TLSLDM)) @@ -8005,14 +8005,14 @@ visl") (const_string "call") (const_string "call_no_delay_slot")))]) -(define_insn "tldo_hix22" +(define_insn "@tldo_hix22" [(set (match_operand:P 0 "register_operand" "=r") (high:P (unspec:P [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDO)))] "TARGET_TLS" "sethi\\t%%tldo_hix22(%a1), %0") -(define_insn "tldo_lox10" +(define_insn "@tldo_lox10" [(set (match_operand:P 0 "register_operand" "=r") (lo_sum:P (match_operand:P 1 "register_operand" "r") (unspec:P [(match_operand 2 "tld_symbolic_operand" "")] @@ -8020,7 +8020,7 @@ visl") "TARGET_TLS" "xor\\t%1, %%tldo_lox10(%a2), %0") -(define_insn "tldo_add" +(define_insn "@tldo_add" [(set (match_operand:P 0 "register_operand" "=r") (plus:P (match_operand:P 1 "register_operand" "r") (unspec:P [(match_operand:P 2 "register_operand" "r") @@ -8029,14 +8029,14 @@ visl") "TARGET_TLS" "add\\t%1, %2, %0, %%tldo_add(%a3)") -(define_insn "tie_hi22" +(define_insn "@tie_hi22" [(set (match_operand:P 0 "register_operand" "=r") (high:P (unspec:P [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE)))] "TARGET_TLS" "sethi\\t%%tie_hi22(%a1), %0") -(define_insn "tie_lo10" +(define_insn "@tie_lo10" [(set (match_operand:P 0 "register_operand" "=r") (lo_sum:P (match_operand:P 1 "register_operand" "r") (unspec:P [(match_operand 2 "tie_symbolic_operand" "")] @@ -8068,7 +8068,7 @@ visl") [(set_attr "type" "load") (set_attr "subtype" "regular")]) -(define_insn "tie_add" +(define_insn "@tie_add" [(set (match_operand:P 0 "register_operand" "=r") (plus:P (match_operand:P 1 "register_operand" "r") (unspec:P [(match_operand:P 2 "register_operand" "r") @@ -8077,14 +8077,14 @@ visl") "TARGET_SUN_TLS" "add\\t%1, %2, %0, %%tie_add(%a3)") -(define_insn "tle_hix22" +(define_insn "@tle_hix22" [(set (match_operand:P 0 "register_operand" "=r") (high:P (unspec:P [(match_operand 1 "tle_symbolic_operand" "")] UNSPEC_TLSLE)))] "TARGET_TLS" "sethi\\t%%tle_hix22(%a1), %0") -(define_insn "tle_lox10" +(define_insn "@tle_lox10" [(set (match_operand:P 0 "register_operand" "=r") (lo_sum:P (match_operand:P 1 "register_operand" "r") (unspec:P [(match_operand 2 "tle_symbolic_operand" "")] @@ -8342,13 +8342,13 @@ visl") operands[1] = gen_rtx_MEM (Pmode, addr); #endif if (TARGET_ARCH64) - emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); + emit_insn (gen_stack_protect_set64 (operands[0], operands[1])); else - emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); + emit_insn (gen_stack_protect_set32 (operands[0], operands[1])); DONE; }) -(define_insn "stack_protect_setsi" +(define_insn "stack_protect_set32" [(set (match_operand:SI 0 "memory_operand" "=m") (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET)) (set (match_scratch:SI 2 "=&r") (const_int 0))] @@ -8357,7 +8357,7 @@ visl") [(set_attr "type" "multi") (set_attr "length" "3")]) -(define_insn "stack_protect_setdi" +(define_insn "stack_protect_set64" [(set (match_operand:DI 0 "memory_operand" "=m") (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET)) (set (match_scratch:DI 2 "=&r") (const_int 0))] @@ -8381,13 +8381,13 @@ visl") if (TARGET_ARCH64) { result = gen_reg_rtx (Pmode); - emit_insn (gen_stack_protect_testdi (result, operands[0], operands[1])); + emit_insn (gen_stack_protect_test64 (result, operands[0], operands[1])); test = gen_rtx_EQ (VOIDmode, result, const0_rtx); emit_jump_insn (gen_cbranchdi4 (test, result, const0_rtx, operands[2])); } else { - emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); + emit_insn (gen_stack_protect_test32 (operands[0], operands[1])); result = gen_rtx_REG (CCmode, SPARC_ICC_REG); test = gen_rtx_EQ (VOIDmode, result, const0_rtx); emit_jump_insn (gen_cbranchcc4 (test, result, const0_rtx, operands[2])); @@ -8395,7 +8395,7 @@ visl") DONE; }) -(define_insn "stack_protect_testsi" +(define_insn "stack_protect_test32" [(set (reg:CC CC_REG) (unspec:CC [(match_operand:SI 0 "memory_operand" "m") (match_operand:SI 1 "memory_operand" "m")] @@ -8407,7 +8407,7 @@ visl") [(set_attr "type" "multi") (set_attr "length" "4")]) -(define_insn "stack_protect_testdi" +(define_insn "stack_protect_test64" [(set (match_operand:DI 0 "register_operand" "=&r") (unspec:DI [(match_operand:DI 1 "memory_operand" "m") (match_operand:DI 2 "memory_operand" "m")] -- cgit v1.1 From bd1cd0d0e0fecc6ac8632c266591767392480746 Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Fri, 23 Apr 2021 19:59:00 +0000 Subject: Remove CC0 This removes CC0 and all directly related infrastructure. CC_STATUS, CC_STATUS_MDEP, CC_STATUS_MDEP_INIT, and NOTICE_UPDATE_CC are deleted and poisoned. CC0 is only deleted (some targets use that name for something else). HAVE_cc0 is automatically generated, and we no longer will do that after this patch. CC_STATUS_INIT is suggested in final.c to also be useful for ports that are not CC0, and at least arm seems to use it for something. So I am leaving that alone, but most targets that have it could remove it. 2021-05-04 Segher Boessenkool * caller-save.c: Remove CC0. * cfgcleanup.c: Remove CC0. * cfgrtl.c: Remove CC0. * combine.c: Remove CC0. * compare-elim.c: Remove CC0. * conditions.h: Remove CC0. * config/h8300/h8300.h: Remove CC0. * config/h8300/h8300-protos.h: Remove CC0. * config/h8300/peepholes.md: Remove CC0. * config/i386/x86-tune-sched.c: Remove CC0. * config/m68k/m68k.c: Remove CC0. * config/rl78/rl78.c: Remove CC0. * config/sparc/sparc.c: Remove CC0. * config/xtensa/xtensa.c: Remove CC0. (gen_conditional_move): Use pc_rtx instead of cc0_rtx in a piece of RTL where that is used as a placeholder only. * cprop.c: Remove CC0. * cse.c: Remove CC0. * cselib.c: Remove CC0. * df-problems.c: Remove CC0. * df-scan.c: Remove CC0. * doc/md.texi: Remove CC0. Adjust an example. * doc/rtl.texi: Remove CC0. Adjust an example. * doc/tm.texi: Regenerate. * doc/tm.texi.in: Remove CC0. * emit-rtl.c: Remove CC0. * final.c: Remove CC0. * fwprop.c: Remove CC0. * gcse-common.c: Remove CC0. * gcse.c: Remove CC0. * genattrtab.c: Remove CC0. * genconfig.c: Remove CC0. * genemit.c: Remove CC0. * genextract.c: Remove CC0. * gengenrtl.c: Remove CC0. * genrecog.c: Remove CC0. * haifa-sched.c: Remove CC0. * ifcvt.c: Remove CC0. * ira-costs.c: Remove CC0. * ira.c: Remove CC0. * jump.c: Remove CC0. * loop-invariant.c: Remove CC0. * lra-constraints.c: Remove CC0. * lra-eliminations.c: Remove CC0. * optabs.c: Remove CC0. * postreload-gcse.c: Remove CC0. * postreload.c: Remove CC0. * print-rtl.c: Remove CC0. * read-rtl-function.c: Remove CC0. * reg-notes.def: Remove CC0. * reg-stack.c: Remove CC0. * reginfo.c: Remove CC0. * regrename.c: Remove CC0. * reload.c: Remove CC0. * reload1.c: Remove CC0. * reorg.c: Remove CC0. * resource.c: Remove CC0. * rtl.c: Remove CC0. * rtl.def: Remove CC0. * rtl.h: Remove CC0. * rtlanal.c: Remove CC0. * sched-deps.c: Remove CC0. * sched-rgn.c: Remove CC0. * shrink-wrap.c: Remove CC0. * simplify-rtx.c: Remove CC0. * system.h: Remove CC0. Poison NOTICE_UPDATE_CC, CC_STATUS_MDEP_INIT, CC_STATUS_MDEP, and CC_STATUS. * target.def: Remove CC0. * valtrack.c: Remove CC0. * var-tracking.c: Remove CC0. --- gcc/config/sparc/sparc.c | 1 - 1 file changed, 1 deletion(-) (limited to 'gcc/config/sparc') diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 3b4d416..b6e66dc 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -8809,7 +8809,6 @@ epilogue_renumber (rtx *where, int test) *where = gen_rtx_REG (GET_MODE (*where), OUTGOING_REGNO (REGNO(*where))); /* fallthrough */ case SCRATCH: - case CC0: case PC: case CONST_INT: case CONST_WIDE_INT: -- cgit v1.1 From c0129e2d489cc0ab419c58c4f8451898c2b5e3ae Mon Sep 17 00:00:00 2001 From: Martin Liska Date: Fri, 19 Mar 2021 10:21:35 +0100 Subject: Use startswith in targets. gcc/ChangeLog: * common/config/aarch64/aarch64-common.c (aarch64_parse_extension): Use startswith function instead of strncmp. * common/config/bfin/bfin-common.c (bfin_handle_option): Likewise. * common/config/riscv/riscv-common.c (riscv_subset_list::parse): Likewise. * config/aarch64/aarch64-sve-builtins-shapes.cc (parse_type): Likewise. * config/aarch64/aarch64.c (aarch64_process_one_target_attr): Likewise. * config/alpha/alpha.c (alpha_elf_section_type_flags): Likewise. * config/arm/aarch-common.c (arm_md_asm_adjust): Likewise. * config/arm/arm.c (arm_file_start): Likewise. (arm_valid_target_attribute_rec): Likewise. (thumb1_md_asm_adjust): Likewise. * config/arm/driver-arm.c (host_detect_local_cpu): Likewise. * config/avr/avr.c (STR_PREFIX_P): Likewise. (avr_set_current_function): Likewise. (avr_handle_addr_attribute): Likewise. (avr_asm_output_aligned_decl_common): Likewise. (avr_asm_named_section): Likewise. (avr_section_type_flags): Likewise. (avr_asm_select_section): Likewise. * config/c6x/c6x.c (c6x_in_small_data_p): Likewise. (c6x_section_type_flags): Likewise. * config/darwin-c.c (darwin_cfstring_ref_p): Likewise. (darwin_objc_declare_unresolved_class_reference): Likewise. (darwin_objc_declare_class_definition): Likewise. * config/darwin.c (indirect_data): Likewise. (darwin_encode_section_info): Likewise. (darwin_objc2_section): Likewise. (darwin_objc1_section): Likewise. (machopic_select_section): Likewise. (darwin_globalize_label): Likewise. (darwin_label_is_anonymous_local_objc_name): Likewise. (darwin_asm_named_section): Likewise. (darwin_asm_output_dwarf_offset): Likewise. * config/frv/frv.c (frv_string_begins_with): Likewise. (frv_in_small_data_p): Likewise. * config/gcn/mkoffload.c (STR): Likewise. (main): Likewise. * config/i386/i386-builtins.c (get_builtin_code_for_version): Likewise. * config/i386/i386-options.c (ix86_option_override_internal): Likewise. * config/i386/i386.c (x86_64_elf_section_type_flags): Likewise. (ix86_md_asm_adjust): Likewise. * config/i386/intelmic-mkoffload.c (STR): Likewise. * config/i386/winnt.c (i386_pe_asm_named_section): Likewise. (i386_pe_file_end): Likewise. * config/ia64/ia64.c (ia64_in_small_data_p): Likewise. (ia64_section_type_flags): Likewise. * config/mips/driver-native.c (host_detect_local_cpu): Likewise. * config/mips/mips.c (mips_handle_interrupt_attr): Likewise. (mips16_stub_function_p): Likewise. (mips_function_rodata_section): Likewise. * config/msp430/msp430.c (msp430_mcu_name): Likewise. (msp430_function_section): Likewise. (msp430_section_type_flags): Likewise. (msp430_expand_helper): Likewise. * config/nios2/nios2.c (nios2_small_section_name_p): Likewise. (nios2_valid_target_attribute_rec): Likewise. * config/nvptx/mkoffload.c (process): Likewise. (STR): Likewise. * config/pa/som.h: Likewise. * config/pdp11/pdp11.c (pdp11_output_ident): Likewise. * config/riscv/riscv.c (riscv_elf_select_rtx_section): Likewise. * config/rs6000/rs6000.c (VTABLE_NAME_P): Likewise. (rs6000_inner_target_options): Likewise. * config/s390/driver-native.c (s390_host_detect_local_cpu): Likewise. * config/sparc/driver-sparc.c (host_detect_local_cpu): Likewise. * config/vax/vax.c (vax_output_int_move): Likewise. * config/vms/vms-ld.c (startswith): Likewise. (process_args): Likewise. (main): Likewise. * config/vms/vms.c: Likewise. --- gcc/config/sparc/driver-sparc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc/config/sparc') diff --git a/gcc/config/sparc/driver-sparc.c b/gcc/config/sparc/driver-sparc.c index f70c53f..698c18e 100644 --- a/gcc/config/sparc/driver-sparc.c +++ b/gcc/config/sparc/driver-sparc.c @@ -148,7 +148,7 @@ host_detect_local_cpu (int argc, const char **argv) return NULL; while (fgets (buf, sizeof (buf), f) != NULL) - if (strncmp (buf, "cpu\t\t:", sizeof ("cpu\t\t:") - 1) == 0) + if (startswith (buf, "cpu\t\t:")) { for (i = 0; cpu_names [i].name; i++) if (strstr (buf, cpu_names [i].name) != NULL) -- cgit v1.1 From 10f36fe50cb3cb75d17903df116719ee2f4e492c Mon Sep 17 00:00:00 2001 From: Kewen Lin Date: Fri, 28 May 2021 00:21:18 -0500 Subject: sparc: Update unexpected empty split condition gcc/ChangeLog: * config/sparc/sparc.md (*snedi_zero_vis3, *neg_snedi_zero_subxc, *plus_snedi_zero, *plus_plus_snedi_zero, *minus_snedi_zero, *minus_minus_snedi_zero): Fix empty split condition. --- gcc/config/sparc/sparc.md | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'gcc/config/sparc') diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index a8d9962..24b76e0 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -855,7 +855,7 @@ (clobber (reg:CCX CC_REG))] "TARGET_ARCH64 && TARGET_VIS3" "#" - "" + "&& 1" [(set (reg:CCXC CC_REG) (compare:CCXC (not:DI (match_dup 1)) (const_int -1))) (set (match_dup 0) (ltu:W (reg:CCXC CC_REG) (const_int 0)))] "" @@ -882,7 +882,7 @@ (clobber (reg:CCX CC_REG))] "TARGET_ARCH64 && TARGET_SUBXC" "#" - "" + "&& 1" [(set (reg:CCXC CC_REG) (compare:CCXC (not:DI (match_dup 1)) (const_int -1))) (set (match_dup 0) (neg:W (ltu:W (reg:CCXC CC_REG) (const_int 0))))] "" @@ -984,7 +984,7 @@ (clobber (reg:CCX CC_REG))] "TARGET_ARCH64 && TARGET_VIS3" "#" - "" + "&& 1" [(set (reg:CCXC CC_REG) (compare:CCXC (not:DI (match_dup 1)) (const_int -1))) (set (match_dup 0) (plus:W (ltu:W (reg:CCXC CC_REG) (const_int 0)) (match_dup 2)))] @@ -1000,7 +1000,7 @@ (clobber (reg:CCX CC_REG))] "TARGET_ARCH64 && TARGET_VIS3" "#" - "" + "&& 1" [(set (reg:CCXC CC_REG) (compare:CCXC (not:DI (match_dup 1)) (const_int -1))) (set (match_dup 0) (plus:W (plus:W (ltu:W (reg:CCXC CC_REG) (const_int 0)) (match_dup 2)) @@ -1048,7 +1048,7 @@ (clobber (reg:CCX CC_REG))] "TARGET_ARCH64 && TARGET_SUBXC" "#" - "" + "&& 1" [(set (reg:CCXC CC_REG) (compare:CCXC (not:DI (match_dup 1)) (const_int -1))) (set (match_dup 0) (minus:W (match_dup 2) (ltu:W (reg:CCXC CC_REG) (const_int 0))))] @@ -1064,7 +1064,7 @@ (clobber (reg:CCX CC_REG))] "TARGET_ARCH64 && TARGET_SUBXC" "#" - "" + "&& 1" [(set (reg:CCXC CC_REG) (compare:CCXC (not:DI (match_dup 1)) (const_int -1))) (set (match_dup 0) (minus:W (minus:W (match_dup 2) (ltu:W (reg:CCXC CC_REG) (const_int 0))) -- cgit v1.1 From fed94fc9e704b0de228499495b7ca4d4c79ef76b Mon Sep 17 00:00:00 2001 From: Eric Botcazou Date: Sun, 6 Jun 2021 23:54:24 +0200 Subject: Reimplement LEAF_REG_REMAP macro for the SPARC The current implementation as an array of chars is indeed a bit awkward so this reimplements it as a function taking and returning an int. gcc/ * config/sparc/sparc-protos.h (order_regs_for_local_alloc): Rename to... (sparc_order_regs_for_local_alloc): ...this. (sparc_leaf_reg_remap): Declare. * config/sparc/sparc.h (ADJUST_REG_ALLOC_ORDER): Adjust. (LEAF_REG_REMAP): Reimplement as call to sparc_leaf_reg_remap. * config/sparc/sparc.c (leaf_reg_remap): Delete. (order_regs_for_local_alloc): Rename to... (sparc_order_regs_for_local_alloc): ...this. (sparc_leaf_reg_remap): New function. (sparc_conditional_register_usage): Do not modify leaf_reg_remap. --- gcc/config/sparc/sparc-protos.h | 3 +- gcc/config/sparc/sparc.c | 67 ++++++++++++++++++++--------------------- gcc/config/sparc/sparc.h | 5 ++- 3 files changed, 37 insertions(+), 38 deletions(-) (limited to 'gcc/config/sparc') diff --git a/gcc/config/sparc/sparc-protos.h b/gcc/config/sparc/sparc-protos.h index ad875cc..8879ac3 100644 --- a/gcc/config/sparc/sparc-protos.h +++ b/gcc/config/sparc/sparc-protos.h @@ -30,7 +30,8 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree); extern unsigned long sparc_type_code (tree); #endif /* TREE_CODE */ -extern void order_regs_for_local_alloc (void); +extern void sparc_order_regs_for_local_alloc (void); +extern int sparc_leaf_reg_remap (int); extern int sparc_initial_elimination_offset (int); extern void sparc_expand_prologue (void); extern void sparc_flat_expand_prologue (void); diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index b6e66dc..04fc80f 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -507,25 +507,6 @@ static const struct processor_costs *sparc_costs = &cypress_costs; ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic) #endif -/* Vector to say how input registers are mapped to output registers. - HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to - eliminate it. You must use -fomit-frame-pointer to get that. */ -char leaf_reg_remap[] = -{ 0, 1, 2, 3, 4, 5, 6, 7, - -1, -1, -1, -1, -1, -1, 14, -1, - -1, -1, -1, -1, -1, -1, -1, -1, - 8, 9, 10, 11, 12, 13, -1, 15, - - 32, 33, 34, 35, 36, 37, 38, 39, - 40, 41, 42, 43, 44, 45, 46, 47, - 48, 49, 50, 51, 52, 53, 54, 55, - 56, 57, 58, 59, 60, 61, 62, 63, - 64, 65, 66, 67, 68, 69, 70, 71, - 72, 73, 74, 75, 76, 77, 78, 79, - 80, 81, 82, 83, 84, 85, 86, 87, - 88, 89, 90, 91, 92, 93, 94, 95, - 96, 97, 98, 99, 100, 101, 102}; - /* Vector, indexed by hard register number, which contains 1 for a register that is allowable in a candidate for leaf function treatment. */ @@ -8863,18 +8844,18 @@ epilogue_renumber (rtx *where, int test) /* Leaf functions and non-leaf functions have different needs. */ -static const int -reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER; +static const int reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER; -static const int -reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER; +static const int reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER; -static const int *const reg_alloc_orders[] = { +static const int *const reg_alloc_orders[] = +{ reg_leaf_alloc_order, - reg_nonleaf_alloc_order}; + reg_nonleaf_alloc_order +}; void -order_regs_for_local_alloc (void) +sparc_order_regs_for_local_alloc (void) { static int last_order_nonleaf = 1; @@ -8886,7 +8867,28 @@ order_regs_for_local_alloc (void) FIRST_PSEUDO_REGISTER * sizeof (int)); } } - + +int +sparc_leaf_reg_remap (int regno) +{ + gcc_checking_assert (regno >= 0); + + /* Do not remap in flat mode. */ + if (TARGET_FLAT) + return regno; + + /* Do not remap global, stack pointer or floating-point registers. */ + if (regno < 8 || regno == STACK_POINTER_REGNUM || regno > SPARC_LAST_INT_REG) + return regno; + + /* Neither out nor local nor frame pointer registers must appear. */ + if ((regno >= 8 && regno <= 23) || regno == HARD_FRAME_POINTER_REGNUM) + return -1; + + /* Remap in to out registers. */ + return regno - 16; +} + /* Return 1 if REG and MEM are legitimate enough to allow the various MEM<-->REG splits to be run. */ @@ -12983,14 +12985,11 @@ sparc_conditional_register_usage (void) fixed_regs[4] = 1; else if (fixed_regs[4] == 2) fixed_regs[4] = 0; + + /* Disable leaf function optimization in flat mode. */ if (TARGET_FLAT) - { - int regno; - /* Disable leaf functions. */ - memset (sparc_leaf_regs, 0, FIRST_PSEUDO_REGISTER); - for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) - leaf_reg_remap [regno] = regno; - } + memset (sparc_leaf_regs, 0, FIRST_PSEUDO_REGISTER); + if (TARGET_VIS) global_regs[SPARC_GSR_REG] = 1; } diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index 4834575..4da5a06 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -965,13 +965,12 @@ extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; 96, 97, 98, 99, /* %fcc0-3 */ \ 100, 0, 14, 30, 31, 101, 102 } /* %icc, %g0, %o6, %i6, %i7, %sfp, %gsr */ -#define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc () +#define ADJUST_REG_ALLOC_ORDER sparc_order_regs_for_local_alloc () extern char sparc_leaf_regs[]; #define LEAF_REGISTERS sparc_leaf_regs -extern char leaf_reg_remap[]; -#define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO]) +#define LEAF_REG_REMAP(REGNO) sparc_leaf_reg_remap (REGNO) /* The class value for index registers, and the one for base regs. */ #define INDEX_REG_CLASS GENERAL_REGS -- cgit v1.1 From 8cdcea51c0fd753e6a652c9b236e91b3a6e0911c Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Mon, 9 Aug 2021 09:06:14 +0200 Subject: gcov: Add TARGET_GCOV_TYPE_SIZE target hook If -fprofile-update=atomic is used, then the target must provide atomic operations for the counters of the type returned by get_gcov_type(). This is a 64-bit type for targets which have a 64-bit long long type. On 32-bit targets this could be an issue since they may not provide 64-bit atomic operations. Allow targets to override the default type size with the new TARGET_GCOV_TYPE_SIZE target hook. If a 32-bit gcov type size is used, then there is currently a warning in libgcov-driver.c in a dead code block due to sizeof (counter) == sizeof (gcov_unsigned_t): libgcc/libgcov-driver.c: In function 'dump_counter': libgcc/libgcov-driver.c:401:46: warning: right shift count >= width of type [-Wshift-count-overflow] 401 | dump_unsigned ((gcov_unsigned_t)(counter >> 32), dump_fn, arg); | ^~ gcc/c-family/ * c-cppbuiltin.c (c_cpp_builtins): Define __LIBGCC_GCOV_TYPE_SIZE if flag_building_libgcc is true. gcc/ * config/sparc/rtemself.h (SPARC_GCOV_TYPE_SIZE): Define. * config/sparc/sparc.c (sparc_gcov_type_size): New. (TARGET_GCOV_TYPE_SIZE): Redefine if SPARC_GCOV_TYPE_SIZE is defined. * coverage.c (get_gcov_type): Use targetm.gcov_type_size(). * doc/tm.texi (TARGET_GCOV_TYPE_SIZE): Add hook under "Misc". * doc/tm.texi.in: Regenerate. * target.def (gcov_type_size): New target hook. * targhooks.c (default_gcov_type_size): New. * targhooks.h (default_gcov_type_size): Declare. * tree-profile.c (gimple_gen_edge_profiler): Use precision of gcov_type_node. (gimple_gen_time_profiler): Likewise. libgcc/ * libgcov.h (gcov_type): Define using __LIBGCC_GCOV_TYPE_SIZE. (gcov_type_unsigned): Likewise. --- gcc/config/sparc/rtemself.h | 2 ++ gcc/config/sparc/sparc.c | 11 +++++++++++ 2 files changed, 13 insertions(+) (limited to 'gcc/config/sparc') diff --git a/gcc/config/sparc/rtemself.h b/gcc/config/sparc/rtemself.h index fa972af..d64ce90 100644 --- a/gcc/config/sparc/rtemself.h +++ b/gcc/config/sparc/rtemself.h @@ -40,3 +40,5 @@ /* Use the default */ #undef LINK_GCC_C_SEQUENCE_SPEC + +#define SPARC_GCOV_TYPE_SIZE 32 diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 04fc80f..06f41d7 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -944,6 +944,17 @@ char sparc_hard_reg_printed[8]; #undef TARGET_ZERO_CALL_USED_REGS #define TARGET_ZERO_CALL_USED_REGS sparc_zero_call_used_regs +#ifdef SPARC_GCOV_TYPE_SIZE +static HOST_WIDE_INT +sparc_gcov_type_size (void) +{ + return SPARC_GCOV_TYPE_SIZE; +} + +#undef TARGET_GCOV_TYPE_SIZE +#define TARGET_GCOV_TYPE_SIZE sparc_gcov_type_size +#endif + struct gcc_target targetm = TARGET_INITIALIZER; /* Return the memory reference contained in X if any, zero otherwise. */ -- cgit v1.1