sparc: support for the SPARC M7 and VIS 4.0

    
gcc/ChangeLog:
    
2016-06-06  Jose E. Marchesi  <jose.marchesi@oracle.com>
    
    	* config/sparc/sparc.md (cpu): Add niagara7 cpu type.
    	Include the M7 SPARC DFA scheduler.
    	New attribute v3pipe.
    	Annotate insns with v3pipe where appropriate.
    	Define cpu_feature vis4.
    	Add lzd instruction type and set it on clzdi_sp64 and clzsi_sp64.
    	Add (V8QI "8") to vbits.
    	Add insns {add,sub}v8qi3
    	Add insns ss{add,sub}v8qi3
    	Add insns us{add,sub}{v8qi,v4hi}3
    	Add insns {min,max}{v8qi,v4hi,v2si}3
    	Add insns {minu,maxu}{v8qi,v4hi,v2si}3
    	Add insns fpcmp{le,gt,ule,ug,ule,ugt}{8,16,32}_vis.
    	* config/sparc/niagara4.md: Add a comment explaining the
    	discrepancy between the documented latenty numbers and the
    	implemented ones.
    	* config/sparc/niagara7.md: New file.
    	* configure.ac (HAVE_AS_SPARC5_VIS4): Define if the assembler
    	supports SPARC5 and VIS 4.0 instructions.
    	* configure: Regenerate.
    	* config.in: Likewise.
    	* config.gcc: niagara7 is a supported cpu in sparc*-*-* targets.
    	* config/sparc/sol2.h (ASM_CPU32_DEFAUILT_SPEC): Set for
    	TARGET_CPU_niagara7.
    	(ASM_CPU64_DEFAULT_SPEC): Likewise.
    	(CPP_CPU_SPEC): Handle niagara7.
    	(ASM_CPU_SPEC): Likewise.
    	* config/sparc/sparc-opts.h (processor_type): Add
    	PROCESSOR_NIAGARA7.
    	(mvis4): New option.
    	* config/sparc/sparc.h (TARGET_CPU_niagara7): Define.
    	(AS_NIAGARA7_FLAG): Define.
    	(ASM_CPU64_DEFAULT_SPEC): Set for niagara7.
    	(CPP_CPU64_DEFAULT_SPEC): Likewise.
    	(CPP_CPU_SPEC): Handle niagara7.
    	(ASM_CPU_SPEC): Likewise.
    	* config/sparc/sparc.c (niagara7_costs): Define.
    	(sparc_option_override): Handle niagara7 and adjust cache-related
    	parameters with better values for niagara cpus.  Also support VIS4.
    	(sparc32_initialize_trampoline): Likewise.
    	(sparc_use_sched_lookahead): Likewise.
    	(sparc_issue_rate): Likewise.
    	(sparc_register_move_cost): Likewise.
    	(dump_target_flag_bits): Support VIS4.
    	(sparc_vis_init_builtins): Likewise.
    	(sparc_builtins): Likewise.
    	* config/sparc/sparc-c.c (sparc_target_macros): Define __VIS__ for
    	VIS4 4.0.
    	* config/sparc/driver-sparc.c (cpu_names): Add SPARC-M7 and
    	UltraSparc M7.
    	* config/sparc/sparc.opt (sparc_processor_type): New value
    	niagara7.
    	* config/sparc/visintrin.h (__attribute__): Prototypes for the
    	VIS4 builtins.
    	* doc/invoke.texi (SPARC Options): Document -mcpu=niagara7 and
    	-mvis4.
    	* doc/extend.texi (SPARC VIS Built-in Functions): Document the
    	VIS4 builtins.
    
gcc/testsuite/ChangeLog:
    
2016-06-06  Jose E. Marchesi  <jose.marchesi@oracle.com>
    
    	* gcc.target/sparc/vis4misc.c: New file.
    	* gcc.target/sparc/fpcmp.c: Likewise.
    	* gcc.target/sparc/fpcmpu.c: Likewise.

From-SVN: r237132

1 files changed, 12 insertions, 2 deletions

diff --git a/gcc/config/sparc/sol2.h b/gcc/config/sparc/sol2.h
index a54e1ec..2a843c5 100644
--- a/gcc/config/sparc/sol2.h
+++ b/gcc/config/sparc/sol2.h
@@ -165,13 +165,22 @@ along with GCC; see the file COPYING3.  If not see
 #define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG AS_NIAGARA4_FLAG
 #endif
 
+#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara7
+#undef CPP_CPU64_DEFAULT_SPEC
+#define CPP_CPU64_DEFAULT_SPEC ""
+#undef ASM_CPU32_DEFAULT_SPEC
+#define ASM_CPU32_DEFAUILT_SPEC AS_SPARC32_FLAG AS_NIAGARA7_FLAG
+#undef ASM_CPU64_DEFAULT_SPEC
+#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG AS_NIAGARA7_FLAG
+#endif
+
 #undef CPP_CPU_SPEC
 #define CPP_CPU_SPEC "\
 %{mcpu=sparclet|mcpu=tsc701:-D__sparclet__} \
 %{mcpu=sparclite|mcpu-f930|mcpu=f934:-D__sparclite__} \
 %{mcpu=v8:" DEF_ARCH32_SPEC("-D__sparcv8") "} \
 %{mcpu=supersparc:-D__supersparc__ " DEF_ARCH32_SPEC("-D__sparcv8") "} \
-%{mcpu=v9|mcpu=ultrasparc|mcpu=ultrasparc3|mcpu=niagara|mcpu=niagara2|mcpu=niagara3|mcpu=niagara4:" DEF_ARCH32_SPEC("-D__sparcv8") "} \
+%{mcpu=v9|mcpu=ultrasparc|mcpu=ultrasparc3|mcpu=niagara|mcpu=niagara2|mcpu=niagara3|mcpu=niagara4|mcpu=niagara7:" DEF_ARCH32_SPEC("-D__sparcv8") "} \
 %{!mcpu*:%(cpp_cpu_default)} \
 "
 
@@ -280,7 +289,8 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
 %{mcpu=niagara2:" DEF_ARCH32_SPEC("-xarch=v8plusb") DEF_ARCH64_SPEC("-xarch=v9b") "} \
 %{mcpu=niagara3:" DEF_ARCH32_SPEC("-xarch=v8plus" AS_NIAGARA3_FLAG) DEF_ARCH64_SPEC("-xarch=v9" AS_NIAGARA3_FLAG) "} \
 %{mcpu=niagara4:" DEF_ARCH32_SPEC(AS_SPARC32_FLAG AS_NIAGARA4_FLAG) DEF_ARCH64_SPEC(AS_SPARC64_FLAG AS_NIAGARA4_FLAG) "} \
-%{!mcpu=niagara4:%{!mcpu=niagara3:%{!mcpu=niagara2:%{!mcpu=niagara:%{!mcpu=ultrasparc3:%{!mcpu=ultrasparc:%{!mcpu=v9:%{mcpu*:" DEF_ARCH32_SPEC("-xarch=v8") DEF_ARCH64_SPEC("-xarch=v9") "}}}}}}}} \
+%{mcpu=niagara7:" DEF_ARCH32_SPEC(AS_SPARC32_FLAG AS_NIAGARA7_FLAG) DEF_ARCH64_SPEC(AS_SPARC64_FLAG AS_NIAGARA7_FLAG) "} \
+%{!mcpu=niagara7:%{!mcpu=niagara4:%{!mcpu=niagara3:%{!mcpu=niagara2:%{!mcpu=niagara:%{!mcpu=ultrasparc3:%{!mcpu=ultrasparc:%{!mcpu=v9:%{mcpu*:" DEF_ARCH32_SPEC("-xarch=v8") DEF_ARCH64_SPEC("-xarch=v9") "}}}}}}}}} \
 %{!mcpu*:%(asm_cpu_default)} \
 "