Make Niagara-4 instruction scheduling more accurate.

	* config/sparc/sparc.md (type attribute): Add new types 'visl'
	(VIS logical operation), 'vismv' (VIS move), and 'pdistn'.  Rename
	'fgm_pdist' to 'pdist'.
	(*movsi_insn): Use vismv and visl.
	(*movdi_insn_sp64): Likewise.
	(*movsf_insn): Likewise.
	(*movdf_insn_sp64): Likewise.
	(*mov<VM32:mode>_insn): Likewise, use 'fsrc2s' instead of 'fsrc1s'.
	(*mov<VM64:mode>_insn_sp64): Likewise, use 'fsrc2s' instead of 'fsrc1s'.
	(*mov<VM64:mode>_insn_sp32): Likewise, use 'fsrc2s' instead of 'fsrc1s'.
	(VIS logical instructions): Mark as visl.
	(pdist_vis): Use 'pdist'.
	(pditsn<mode>_vis): Use 'pdistn'.
	* config/sparc/ultra1_2.md: Adjust for new VIS attribute types.
	* config/sparc/ultra3.md: Likewise.
	* config/sparc/niagara.md: Likewise.
	* config/sparc/niagara2.md: Likewise.
	* config/sparc/niagara4.md: Add cpu units "n4_slot2" and
	"n4_load_store" for special store scheduling.  Use them in load
	and store reservations.  Integer divide and multiply can only
	issue in slot-1.  Represent 1-cycle VIS moves and 3-cycle VIS
	logic operations.

From-SVN: r192286

1 files changed, 40 insertions, 9 deletions

diff --git a/gcc/config/sparc/niagara4.md b/gcc/config/sparc/niagara4.md
index f1f83b6..272c8ff 100644
--- a/gcc/config/sparc/niagara4.md
+++ b/gcc/config/sparc/niagara4.md
@@ -19,12 +19,14 @@
 
 (define_automaton "niagara4_0")
 
-(define_cpu_unit "n4_slot0,n4_slot1" "niagara4_0")
-(define_reservation "n4_single_issue" "n4_slot0 + n4_slot1")
+(define_cpu_unit "n4_slot0,n4_slot1,n4_slot2" "niagara4_0")
+(define_reservation "n4_single_issue" "n4_slot0 + n4_slot1 + n4_slot2")
+
+(define_cpu_unit "n4_load_store" "niagara4_0")
 
 (define_insn_reservation "n4_single" 1
   (and (eq_attr "cpu" "niagara4")
-    (eq_attr "type" "multi,savew,flushw,iflush,trap,gsr"))
+    (eq_attr "type" "multi,savew,flushw,iflush,trap"))
   "n4_single_issue")
 
 (define_insn_reservation "n4_integer" 1
@@ -35,22 +37,22 @@
 (define_insn_reservation "n4_imul" 12
   (and (eq_attr "cpu" "niagara4")
     (eq_attr "type" "imul"))
-  "(n4_slot0 | n4_slot1), nothing*11")
+  "n4_slot1, nothing*11")
 
 (define_insn_reservation "n4_idiv" 35
   (and (eq_attr "cpu" "niagara4")
     (eq_attr "type" "idiv"))
-  "(n4_slot0 | n4_slot1), nothing*34")
+  "n4_slot1, nothing*34")
 
 (define_insn_reservation "n4_load" 5
   (and (eq_attr "cpu" "niagara4")
     (eq_attr "type" "load,fpload,sload"))
-  "n4_slot0, nothing*4")
+  "(n4_slot0 + n4_load_store), nothing*4")
 
 (define_insn_reservation "n4_store" 1
   (and (eq_attr "cpu" "niagara4")
     (eq_attr "type" "store,fpstore"))
-  "n4_slot0")
+  "(n4_slot0 | n4_slot2) + n4_load_store")
 
 (define_insn_reservation "n4_cti" 2
   (and (eq_attr "cpu" "niagara4")
@@ -67,9 +69,38 @@
     (eq_attr "type" "array,edge,edgen"))
   "n4_slot1, nothing*11")
 
-(define_insn_reservation "n4_vis" 11
+(define_insn_reservation "n4_vis_move_1cycle" 1
+  (and (eq_attr "cpu" "niagara4")
+    (and (eq_attr "type" "vismv")
+      (eq_attr "fptype" "double")))
+  "n4_slot1")
+
+(define_insn_reservation "n4_vis_move_11cycle" 11
+  (and (eq_attr "cpu" "niagara4")
+    (and (eq_attr "type" "vismv")
+      (eq_attr "fptype" "single")))
+  "n4_slot1, nothing*10")
+
+(define_insn_reservation "n4_vis_logical" 3
+  (and (eq_attr "cpu" "niagara4")
+    (and (eq_attr "type" "visl,pdistn")
+      (eq_attr "fptype" "double")))
+  "n4_slot1, nothing*2")
+
+(define_insn_reservation "n4_vis_logical_11cycle" 11
+  (and (eq_attr "cpu" "niagara4")
+    (and (eq_attr "type" "visl")
+      (eq_attr "fptype" "single")))
+  "n4_slot1, nothing*10")
+
+(define_insn_reservation "n4_vis_fga" 11
+  (and (eq_attr "cpu" "niagara4")
+    (eq_attr "type" "fga,gsr"))
+  "n4_slot1, nothing*10")
+
+(define_insn_reservation "n4_vis_fgm" 11
   (and (eq_attr "cpu" "niagara4")
-    (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_pdist"))
+    (eq_attr "type" "fgm_pack,fgm_mul,pdist"))
   "n4_slot1, nothing*10")
 
 (define_insn_reservation "n4_fpdivs" 24