defaults.h (VECTOR_MODE_SUPPORTED_P): Remove macro.

2004-08-23  Eric Christopher  <echristo@redhat.com>

	* defaults.h (VECTOR_MODE_SUPPORTED_P): Remove macro.
	* system.h (VECTOR_MODE_SUPPORTED_P): Poison.
	* target-def.h (TARGET_VECTOR_MODE_SUPPORTED_P): Define.
	* target.h: Ditto.
	* hooks.h: Include machmode.h.
	(hook_bool_mode_false): Declare.
	* hooks.c (hook_bool_mode_false): Define.
	* expr.c (vector_mode_valid_p): Use targetm.vector_mode_supported_p.
	* stor-layout.c (layout_type): Ditto.
	* config/alpha/alpha.c (alpha_vector_mode_supported_p): New function.
	Define to target macro.
	* config/alpha/alpha.h (VECTOR_MODE_SUPPORTED_P): Delete.
	* config/arm/arm.c: Ditto. Use.
	* config/arm/arm.h: Ditto.
	* config/arm/arm-protos.h: Ditto.
	* config/i386/i386.c: Ditto.
	* config/i386/i386.h: Ditto.
	* config/rs6000/rs6000.c: Ditto.
	* config/rs6000/rs6000.h: Ditto.
	* config/sh/sh.c: Ditto.
	* config/sh/sh.h: Ditto.
	* config/sh/sh-protos.h: Ditto.
	* config/sh/sh.md: Use.
	* doc/tm.texi: Move documentation for VECTOR_MODE_SUPPORTED_P
	to TARGET_VECTOR_MODE_SUPPORTED_P.

2004-08-23  Eric Christopher  <echristo@redhat.com>

	* trans-types.c (gfc_type_for_mode): Remove VECTOR_TYPE_SUPPORTED_P
	usage. Use build_vector_type_for_mode for vector types.

From-SVN: r86453

4 files changed, 118 insertions, 103 deletions

diff --git a/gcc/config/sh/sh-protos.h b/gcc/config/sh/sh-protos.h
index d5ddb7b..a3a19f6 100644
--- a/gcc/config/sh/sh-protos.h
+++ b/gcc/config/sh/sh-protos.h
@@ -101,6 +101,7 @@ extern int sh_can_redirect_branch (rtx, rtx);
 extern void sh_expand_unop_v2sf (enum rtx_code, rtx, rtx);
 extern void sh_expand_binop_v2sf (enum rtx_code, rtx, rtx, rtx);
 extern int sh_expand_t_scc (enum rtx_code code, rtx target);
+extern bool sh_vector_mode_supported_p (enum machine_mode);
 #ifdef TREE_CODE
 extern void sh_va_start (tree, rtx);
 #endif /* TREE_CODE */
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index 254aef5..1c539e8 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -2,7 +2,7 @@
    Copyright (C) 1993, 1994, 1995, 1997, 1997, 1998, 1999, 2000, 2001, 2002,
    2003, 2004 Free Software Foundation, Inc.
    Contributed by Steve Chamberlain (sac@cygnus.com).
-   Improved by Jim Wilson (wilson@cygnus.com). 
+   Improved by Jim Wilson (wilson@cygnus.com).
 
 This file is part of GCC.
 
@@ -242,7 +242,7 @@ static int sh_reorder (FILE *, int, rtx *, int *, int);
 static int sh_reorder2 (FILE *, int, rtx *, int *, int);
 static void sh_md_init (FILE *, int, int);
 static int sh_variable_issue (FILE *, int, rtx, int);
-  
+
 static bool sh_function_ok_for_sibcall (tree, tree);
 
 static bool sh_cannot_modify_jumps_p (void);
@@ -326,11 +326,11 @@ static bool sh_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
 
 /* The next 5 hooks have been implemented for reenabling sched1.  With the
    help of these macros we are limiting the movement of insns in sched1 to
-   reduce the register pressure.  The overall idea is to keep count of SImode 
+   reduce the register pressure.  The overall idea is to keep count of SImode
    and SFmode regs required by already scheduled insns. When these counts
    cross some threshold values; give priority to insns that free registers.
    The insn that frees registers is most likely to be the insn with lowest
-   LUID (original insn order); but such an insn might be there in the stalled 
+   LUID (original insn order); but such an insn might be there in the stalled
    queue (Q) instead of the ready queue (R).  To solve this, we skip cycles
    upto a max of 8 cycles so that such insns may move from Q -> R.
 
@@ -340,7 +340,7 @@ static bool sh_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
    scheduler; it is called inside the sched_init function just after
    find_insn_reg_weights function call. It is used to calculate the SImode
    and SFmode weights of insns of basic blocks; much similar to what
-   find_insn_reg_weights does. 
+   find_insn_reg_weights does.
    TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.
 
    TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is
@@ -444,6 +444,9 @@ static bool sh_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
 #define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr
 
+#undef TARGET_VECTOR_MODE_SUPPORTED_P
+#define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p
+
 #undef TARGET_PCH_VALID_P
 #define TARGET_PCH_VALID_P sh_pch_valid_p
 
@@ -658,7 +661,7 @@ print_operand (FILE *stream, rtx x, int code)
 
       fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
       break;
-      
+
     case 'N':
       if (x == CONST0_RTX (GET_MODE (x)))
 	{
@@ -711,7 +714,7 @@ print_operand (FILE *stream, rtx x, int code)
 	case MEM:
 	  output_address (XEXP (x, 0));
 	  break;
-	  
+
 	case CONST:
 	  if (TARGET_SHMEDIA
 	      && GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
@@ -1003,7 +1006,7 @@ prepare_move_operands (rtx operands[], enum machine_mode mode)
 	{
 	  rtx tga_op1, tga_ret, tmp, tmp2;
 
-	  
+
 	  switch (tls_kind)
 	    {
 	    case TLS_MODEL_GLOBAL_DYNAMIC:
@@ -1370,11 +1373,11 @@ output_branch (int logic, rtx insn, rtx *operands)
 	  int label = lf++;
 	  /* The call to print_slot will clobber the operands.  */
 	  rtx op0 = operands[0];
-    
+
 	  /* If the instruction in the delay slot is annulled (true), then
 	     there is no delay slot where we can put it now.  The only safe
 	     place for it is after the label.  final will do that by default.  */
-    
+
 	  if (final_sequence
 	      && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
 	    {
@@ -1384,11 +1387,11 @@ output_branch (int logic, rtx insn, rtx *operands)
 	    }
 	  else
 	    asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
-    
+
 	  output_asm_insn ("bra\t%l0", &op0);
 	  fprintf (asm_out_file, "\tnop\n");
 	  (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
-    
+
 	  return "";
 	}
       /* When relaxing, handle this like a short branch.  The linker
@@ -1420,7 +1423,7 @@ output_branch (int logic, rtx insn, rtx *operands)
     case 4:
       {
 	char buffer[10];
-	
+
 	sprintf (buffer, "b%s%ss\t%%l0",
 		 logic ? "t" : "f",
 		 ASSEMBLER_DIALECT ? "/" : ".");
@@ -1495,7 +1498,7 @@ sh_file_start (void)
   fputs ("\t.section .directive, \"SM\", @progbits, 1\n", asm_out_file);
   fputs ("\t.asciz \"#<SYMEDIT>#\\n\"\n", asm_out_file);
 #endif
-  
+
   if (TARGET_ELF)
     /* We need to show the text section with the proper
        attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
@@ -1599,7 +1602,7 @@ static const short shift_amounts[32][5] = {
 /* Likewise, but for shift amounts < 16, up to three highmost bits
    might be clobbered.  This is typically used when combined with some
    kind of sign or zero extension.  */
-   
+
 static const char ext_shift_insns[]    =
   { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
 
@@ -1963,7 +1966,7 @@ gen_ashift_hi (int type, int n, rtx reg)
 
 /* Output RTL to split a constant shift into its component SH constant
    shift instructions.  */
-   
+
 void
 gen_shifty_op (int code, rtx *operands)
 {
@@ -1972,7 +1975,7 @@ gen_shifty_op (int code, rtx *operands)
 
   /* Truncate the shift count in case it is out of bounds.  */
   value = value & 0x1f;
- 
+
   if (value == 31)
     {
       if (code == LSHIFTRT)
@@ -2006,7 +2009,7 @@ gen_shifty_op (int code, rtx *operands)
   for (i = 0; i < max; i++)
     gen_ashift (code, shift_amounts[value][i], operands[0]);
 }
-   
+
 /* Same as above, but optimized for values where the topmost bits don't
    matter.  */
 
@@ -2359,7 +2362,7 @@ gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
 	  || reload_in_progress || reload_completed)
 	{
 	  rtx operands[3];
-  
+
 	  /* Cases 3 and 4 should be handled by this split
 	     only while combining  */
 	  if (kind > 2)
@@ -2658,7 +2661,7 @@ gen_datalabel_ref (rtx sym)
 			  gen_rtx_UNSPEC (GET_MODE (sym),
 					  gen_rtvec (1, sym),
 					  UNSPEC_DATALABEL));
-    
+
   if (GET_CODE (sym) != SYMBOL_REF)
     abort ();
 
@@ -2955,7 +2958,7 @@ dump_table (rtx start, rtx barrier)
 
       pool_size = 0;
     }
-  
+
   for (i = 0; i < pool_size; i++)
     {
       pool_node *p = &pool_vector[i];
@@ -3513,7 +3516,7 @@ regs_used (rtx x, int is_dest)
     case SUBREG:
       {
 	rtx y = SUBREG_REG (x);
-     
+
 	if (GET_CODE (y) != REG)
 	  break;
 	if (REGNO (y) < 16)
@@ -3568,7 +3571,7 @@ regs_used (rtx x, int is_dest)
    pass 1.  Pass 2 if a definite blocking insn is needed.
    -1 is used internally to avoid deep recursion.
    If a blocking instruction is made or recognized, return it.  */
-   
+
 static rtx
 gen_block_redirect (rtx jump, int addr, int need_block)
 {
@@ -3611,11 +3614,11 @@ gen_block_redirect (rtx jump, int addr, int need_block)
 	 it would cause trouble if an interrupt occurred.  */
       unsigned try = 0x7fff, used;
       int jump_left = flag_expensive_optimizations + 1;
-    
+
       /* It is likely that the most recent eligible instruction is wanted for
 	 the delay slot.  Therefore, find out which registers it uses, and
 	 try to avoid using them.  */
-	 
+
       for (scan = jump; (scan = PREV_INSN (scan)); )
 	{
 	  enum rtx_code code;
@@ -3670,7 +3673,7 @@ gen_block_redirect (rtx jump, int addr, int need_block)
      threading with a jump beyond the delay slot insn.
      Don't check if we are called recursively; the jump has been or will be
      checked in a different invocation then.  */
-	
+
   else if (optimize && need_block >= 0)
     {
       rtx next = next_active_insn (next_active_insn (dest));
@@ -3705,7 +3708,7 @@ gen_block_redirect (rtx jump, int addr, int need_block)
 	 Hence, after delay slot scheduling, we'll have to expect
 	 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
 	 the jump.  */
-	 
+
       INSN_LOCATOR (insn) = INSN_LOCATOR (jump);
       INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
       return insn;
@@ -3833,7 +3836,7 @@ barrier_align (rtx barrier_or_label)
 {
   rtx next = next_real_insn (barrier_or_label), pat, prev;
   int slot, credit, jump_to_next = 0;
- 
+
   if (! next)
     return 0;
 
@@ -3875,11 +3878,11 @@ barrier_align (rtx barrier_or_label)
 	 an alignment, against that of fetching unneeded insn in front of the
 	 branch target when there is no alignment.  */
 
-      /* There are two delay_slot cases to consider.  One is the simple case 
-	 where the preceding branch is to the insn beyond the barrier (simple 
-	 delay slot filling), and the other is where the preceding branch has 
-	 a delay slot that is a duplicate of the insn after the barrier 
-	 (fill_eager_delay_slots) and the branch is to the insn after the insn 
+      /* There are two delay_slot cases to consider.  One is the simple case
+	 where the preceding branch is to the insn beyond the barrier (simple
+	 delay slot filling), and the other is where the preceding branch has
+	 a delay slot that is a duplicate of the insn after the barrier
+	 (fill_eager_delay_slots) and the branch is to the insn after the insn
 	 after the barrier.  */
 
       /* PREV is presumed to be the JUMP_INSN for the barrier under
@@ -3897,7 +3900,7 @@ barrier_align (rtx barrier_or_label)
 	  if (GET_CODE (PATTERN (prev)) == SEQUENCE)
 	    {
 	      prev = XVECEXP (PATTERN (prev), 0, 1);
-	      if (INSN_UID (prev) == INSN_UID (next)) 
+	      if (INSN_UID (prev) == INSN_UID (next))
 		{
 	  	  /* Delay slot was filled with insn at jump target.  */
 		  jump_to_next = 1;
@@ -3924,8 +3927,8 @@ barrier_align (rtx barrier_or_label)
 	      /* There is no upper bound on redundant instructions
 		 that might have been skipped, but we must not put an
 		 alignment where none had been before.  */
-	      || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),	    
-		  (INSN_P (x) 
+	      || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
+		  (INSN_P (x)
 		   && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
 		       || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch
 		       || INSN_CODE (x) == CODE_FOR_stuff_delay_slot))))
@@ -3938,7 +3941,7 @@ barrier_align (rtx barrier_or_label)
 	    }
 	}
     }
-  
+
   return align_jumps_log;
 }
 
@@ -4501,7 +4504,7 @@ split_branches (rtx first)
 	if (type == TYPE_CBRANCH)
 	  {
 	    rtx next, beyond;
-    
+
 	    if (get_attr_length (insn) > 4)
 	      {
 		rtx src = SET_SRC (PATTERN (insn));
@@ -4510,7 +4513,7 @@ split_branches (rtx first)
 		rtx label = 0;
 		int dest_uid = get_dest_uid (olabel, max_uid);
 		struct far_branch *bp = uid_branch[dest_uid];
-    
+
 		/* redirect_jump needs a valid JUMP_LABEL, and it might delete
 		   the label if the LABEL_NUSES count drops to zero.  There is
 		   always a jump_optimize pass that sets these values, but it
@@ -4578,7 +4581,7 @@ split_branches (rtx first)
 		beyond
 		  = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
 					    0));
-	
+
 		if (beyond
 		    && (GET_CODE (beyond) == JUMP_INSN
 			|| ((beyond = next_active_insn (beyond))
@@ -4592,7 +4595,7 @@ split_branches (rtx first)
 		  gen_block_redirect (beyond,
 				      INSN_ADDRESSES (INSN_UID (beyond)), 1);
 	      }
-    
+
 	    next = next_active_insn (insn);
 
 	    if ((GET_CODE (next) == JUMP_INSN
@@ -4995,7 +4998,7 @@ pop (int rn)
     x = gen_pop_e (gen_rtx_REG (SFmode, rn));
   else
     x = gen_pop (gen_rtx_REG (SImode, rn));
-    
+
   x = emit_insn (x);
   REG_NOTES (x)
     = gen_rtx_EXPR_LIST (REG_INC,
@@ -5056,7 +5059,7 @@ shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask)
       stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
   return stack_space;
 }
-   
+
 /* Decide whether we should reserve space for callee-save target registers,
    in case target register allocation wants to use them.  REGS_SAVED is
    the space, in bytes, that is already required for register saves.
@@ -5298,7 +5301,7 @@ typedef struct save_schedule_s
    use reverse order.  Returns the last entry written to (not counting
    the delimiter).  OFFSET_BASE is a number to be added to all offset
    entries.  */
-   
+
 static save_entry *
 sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
 		    int offset_base)
@@ -5478,7 +5481,7 @@ sh_expand_prologue (void)
 	      int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
 	      rtx insn;
 
-	      if (i >= (NPARM_REGS(SImode) 
+	      if (i >= (NPARM_REGS(SImode)
 			- current_function_args_info.arg_count[(int) SH_ARG_INT]
 			))
 		break;
@@ -5497,7 +5500,7 @@ sh_expand_prologue (void)
      that already happens to be at the function start into the prologue.  */
   if (target_flags != save_flags && ! current_function_interrupt)
     emit_insn (gen_toggle_sz ());
-    
+
   if (TARGET_SH5)
     {
       int offset_base, offset;
@@ -5605,7 +5608,7 @@ sh_expand_prologue (void)
 			       GEN_INT (offset - offset_in_r0)));
 	      offset_in_r0 += offset - offset_in_r0;
 	    }
-					      
+
 	  if (pre_dec != NULL_RTX)
 	    {
 	      if (! sp_in_r0)
@@ -5667,7 +5670,7 @@ sh_expand_prologue (void)
 	    insn = emit_move_insn (mem_rtx, reg_rtx);
 	    RTX_FRAME_RELATED_P (insn) = 1;
 
-	    if (TARGET_SHCOMPACT && (offset_in_r0 != -1)) 
+	    if (TARGET_SHCOMPACT && (offset_in_r0 != -1))
 	      {
 		rtx reg_rtx = gen_rtx_REG (mode, reg);
 		rtx set, note_rtx;
@@ -5880,12 +5883,12 @@ sh_expand_epilogue (bool sibcall_p)
 		post_inc = NULL_RTX;
 
 		break;
-		
+
 	      post_inc_ok:
 		mem_rtx = NULL_RTX;
 	      }
 	  while (0);
-	  
+
 	  if (mem_rtx != NULL_RTX)
 	    goto addr_ok;
 
@@ -5902,7 +5905,7 @@ sh_expand_epilogue (bool sibcall_p)
 			       GEN_INT (offset - offset_in_r0)));
 	      offset_in_r0 += offset - offset_in_r0;
 	    }
-	      
+
 	  if (post_inc != NULL_RTX)
 	    {
 	      if (! sp_in_r0)
@@ -5912,7 +5915,7 @@ sh_expand_epilogue (bool sibcall_p)
 				  (Pmode, r0, stack_pointer_rtx));
 		  sp_in_r0 = 1;
 		}
-	      
+
 	      mem_rtx = post_inc;
 
 	      offset_in_r0 += GET_MODE_SIZE (mode);
@@ -5967,7 +5970,7 @@ sh_expand_epilogue (bool sibcall_p)
       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
 	{
 	  int j = (FIRST_PSEUDO_REGISTER - 1) - i;
-  
+
 	  if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD
 	      && hard_regs_intersect_p (&live_regs_mask,
 					&reg_class_contents[DF_REGS]))
@@ -6064,7 +6067,7 @@ sh_set_return_address (rtx ra, rtx tmp)
       int offset;
       save_schedule schedule;
       save_entry *entry;
-      
+
       entry = sh5_schedule_saves (&live_regs_mask, &schedule, 0);
       offset = entry[1].offset;
       for (; entry->mode != VOIDmode; entry--)
@@ -6146,7 +6149,7 @@ sh_builtin_saveregs (void)
       if (TARGET_SHCOMPACT)
 	return const0_rtx;
     }
-  
+
   if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
     {
       error ("__builtin_saveregs not supported by this subtarget");
@@ -6212,7 +6215,7 @@ sh_builtin_saveregs (void)
 				 GEN_INT (-2 * UNITS_PER_WORD)));
 	  mem = gen_rtx_MEM (DFmode, fpregs);
 	  set_mem_alias_set (mem, alias_set);
-	  emit_move_insn (mem, 
+	  emit_move_insn (mem,
 			  gen_rtx_REG (DFmode, BASE_ARG_REG (DFmode) + regno));
 	}
       regno = first_floatreg;
@@ -6668,7 +6671,7 @@ sh_function_arg (CUMULATIVE_ARGS *ca, enum machine_mode mode,
       return gen_rtx_REG (mode, regno);
 
     }
-  
+
   if (TARGET_SH5)
     {
       if (mode == VOIDmode && TARGET_SHCOMPACT)
@@ -6706,7 +6709,7 @@ sh_function_arg (CUMULATIVE_ARGS *ca, enum machine_mode mode,
 
   return 0;
 }
- 
+
 /* Update the data in CUM to advance over an argument
    of mode MODE and data type TYPE.
    (TYPE is null for libcalls where that information may not be
@@ -6983,7 +6986,7 @@ initial_elimination_offset (int from, int to)
 	  int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
 	  save_schedule schedule;
 	  save_entry *entry;
-	  
+
 	  n += total_auto_space;
 
 	  /* If it wasn't saved, there's not much we can do.  */
@@ -7074,7 +7077,7 @@ const struct attribute_spec sh_attribute_table[] =
   /* Symbian support adds three new attributes:
      dllexport - for exporting a function/variable that will live in a dll
      dllimport - for importing a function/variable from a dll
-     
+
      Microsoft allows multiple declspecs in one __declspec, separating
      them with spaces.  We do NOT support this.  Instead, use __declspec
      multiple times.  */
@@ -7237,7 +7240,7 @@ sh_pch_valid_p (const void *data_p, size_t len)
   int flag_mask
     = (SH1_BIT | SH2_BIT | SH3_BIT | SH_E_BIT | HARD_SH4_BIT | FPU_SINGLE_BIT
        | SH4_BIT | HITACHI_BIT | LITTLE_ENDIAN_BIT);
-  
+
   /* -fpic and -fpie also usually make a PCH invalid.  */
   if (data[0] != flag_pic)
     return _("created and used with different settings of -fpic");
@@ -7267,7 +7270,7 @@ sh_pch_valid_p (const void *data_p, size_t len)
     }
   data += sizeof (target_flags);
   len -= sizeof (target_flags);
-  
+
   /* Check string options.  */
 #ifdef TARGET_OPTIONS
   for (i = 0; i < ARRAY_SIZE (target_options); i++)
@@ -7288,7 +7291,7 @@ sh_pch_valid_p (const void *data_p, size_t len)
 #endif
 
   return NULL;
-  
+
  make_message:
   {
     char *r;
@@ -7903,7 +7906,7 @@ sh_const_vec (rtx v, enum machine_mode mode)
 }
 
 /* Return the destination address of a branch.  */
-   
+
 static int
 branch_dest (rtx branch)
 {
@@ -8093,7 +8096,7 @@ f(double a)
    remove assignments that are dead due to a following assignment in the
    same basic block.  */
 
-static void 
+static void
 mark_use (rtx x, rtx *reg_set_block)
 {
   enum rtx_code code;
@@ -8176,7 +8179,7 @@ get_free_reg (HARD_REG_SET regs_live)
   abort ();
 }
 
-/* This function will set the fpscr from memory. 
+/* This function will set the fpscr from memory.
    MODE is the mode we are setting it to.  */
 void
 fpscr_set_from_mem (int mode, HARD_REG_SET regs_live)
@@ -8222,7 +8225,7 @@ sh_insn_length_adjustment (rtx insn)
     return 2;
 
   /* sh-dsp parallel processing insn take four bytes instead of two.  */
-     
+
   if (GET_CODE (insn) == INSN)
     {
       int sum = 0;
@@ -8418,7 +8421,7 @@ mark_constant_pool_use (rtx x)
 /* Return true if it's possible to redirect BRANCH1 to the destination
    of an unconditional jump BRANCH2.  We only want to do this if the
    resulting branch will have a short displacement.  */
-int 
+int
 sh_can_redirect_branch (rtx branch1, rtx branch2)
 {
   if (flag_expensive_optimizations && simplejump_p (branch2))
@@ -8426,21 +8429,21 @@ sh_can_redirect_branch (rtx branch1, rtx branch2)
       rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
       rtx insn;
       int distance;
-      
-      for (distance = 0, insn = NEXT_INSN (branch1); 
-	   insn && distance < 256; 
+
+      for (distance = 0, insn = NEXT_INSN (branch1);
+	   insn && distance < 256;
 	   insn = PREV_INSN (insn))
 	{
-	  if (insn == dest)    
+	  if (insn == dest)
 	    return 1;
 	  else
 	    distance += get_attr_length (insn);
 	}
-      for (distance = 0, insn = NEXT_INSN (branch1); 
-	   insn && distance < 256; 
+      for (distance = 0, insn = NEXT_INSN (branch1);
+	   insn && distance < 256;
 	   insn = NEXT_INSN (insn))
 	{
-	  if (insn == dest)    
+	  if (insn == dest)
 	    return 1;
 	  else
 	    distance += get_attr_length (insn);
@@ -8706,7 +8709,7 @@ rank_for_reorder (const void *x, const void *y)
   if (SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2))
     return SCHED_GROUP_P (tmp2) ? 1 : -1;
 
-  /* If insns are equally good, sort by INSN_LUID (original insn order), This 
+  /* If insns are equally good, sort by INSN_LUID (original insn order), This
      minimizes instruction movement, thus minimizing sched's effect on
      register pressure.  */
   return INSN_LUID (tmp) - INSN_LUID (tmp2);
@@ -8861,7 +8864,7 @@ sh_reorder (FILE *dump ATTRIBUTE_UNUSED,
 }
 
 /* Skip cycles if the current register pressure is high.  */
-static int 
+static int
 sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
 	     int sched_verbose ATTRIBUTE_UNUSED,
 	     rtx *ready ATTRIBUTE_UNUSED,
@@ -8871,7 +8874,7 @@ sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
   if (reload_completed)
     return cached_can_issue_more;
 
-  if (high_pressure(SFmode) || high_pressure (SImode)) 
+  if (high_pressure(SFmode) || high_pressure (SImode))
     skip_cycles = 1;
 
   return cached_can_issue_more;
@@ -8879,11 +8882,11 @@ sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
 
 /* Skip cycles without sorting the ready queue. This will move insn from
    Q->R. If this is the last cycle we are skipping; allow sorting of ready
-   queue by sh_reorder.  */ 
+   queue by sh_reorder.  */
 
-/* Generally, skipping these many cycles are sufficient for all insns to move 
-   from Q -> R.  */ 
-#define MAX_SKIPS 8 
+/* Generally, skipping these many cycles are sufficient for all insns to move
+   from Q -> R.  */
+#define MAX_SKIPS 8
 
 static int
 sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED,
@@ -8896,7 +8899,7 @@ sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED,
   if (reload_completed)
     return 0;
 
-  if (skip_cycles) 
+  if (skip_cycles)
     {
       if ((clock_var - last_clock_var) < MAX_SKIPS)
 	{
@@ -8943,7 +8946,7 @@ sh_ms_bitfield_layout_p (tree record_type ATTRIBUTE_UNUSED)
   return (TARGET_SH5 || TARGET_HITACHI || sh_attr_renesas_p (record_type));
 }
 
-/* 
+/*
    On the SH1..SH4, the trampoline looks like
    2 0002 D202     	   	mov.l	l2,r2
    1 0000 D301     		mov.l	l1,r3
@@ -9037,7 +9040,7 @@ sh_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
       emit_move_insn (gen_rtx_MEM (Pmode,
 				   plus_constant (tramp,
 						  fixed_len
-						  + GET_MODE_SIZE (Pmode))), 
+						  + GET_MODE_SIZE (Pmode))),
 		      cxt);
       emit_insn (gen_ic_invalidate_line (tramp));
       return;
@@ -9119,7 +9122,7 @@ sh_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
 static bool
 sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
 {
-  return (decl 
+  return (decl
 	  && (! TARGET_SHCOMPACT
 	      || current_function_args_info.stack_regs == 0)
 	  && ! sh_cfun_interrupt_handler_p ());
@@ -9338,6 +9341,26 @@ sh_media_init_builtins (void)
     }
 }
 
+/* Implements target hook vector_mode_supported_p.  */
+bool
+sh_vector_mode_supported_p (enum machine_mode mode)
+{
+  if (TARGET_FPU_ANY
+      && ((mode == V2SFmode)
+	  || (mode == V4SFmode)
+	  || (mode == V16SFmode)))
+    return true;
+
+  else if (TARGET_SHMEDIA
+	   && ((mode == V8QImode)
+	       || (mode == V2HImode)
+	       || (mode == V4HImode)
+	       || (mode == V2SImode)))
+    return true;
+
+  return false;
+}
+
 static void
 sh_init_builtins (void)
 {
@@ -9538,7 +9561,7 @@ sh_register_move_cost (enum machine_mode mode,
 
   if ((dstclass == FPUL_REGS
        && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
-      || (srcclass == FPUL_REGS		
+      || (srcclass == FPUL_REGS
 	  && (dstclass == PR_REGS || dstclass == MAC_REGS)))
     return 7;
 
@@ -9613,7 +9636,7 @@ sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
 
   /* Find the "this" pointer.  We have such a wide range of ABIs for the
      SH that it's best to do this completely machine independently.
-     "this" is passed as first argument, unless a structure return pointer 
+     "this" is passed as first argument, unless a structure return pointer
      comes first, in which case "this" comes second.  */
   INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0, 1);
 #ifndef PCC_STATIC_STRUCT_RETURN
@@ -9621,7 +9644,7 @@ sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
     structure_value_byref = 1;
 #endif /* not PCC_STATIC_STRUCT_RETURN */
   if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0)
-    { 
+    {
       tree ptype = build_pointer_type (TREE_TYPE (funtype));
 
       FUNCTION_ARG_ADVANCE (cum, Pmode, ptype, 1);
@@ -9877,7 +9900,7 @@ check_use_sfunc_addr (rtx insn, rtx reg)
 	break;
       if (! INSN_P (insn))
 	continue;
-	
+
       if (GET_CODE (PATTERN (insn)) == SEQUENCE)
 	insn = XVECEXP (PATTERN (insn), 0, 0);
       if (GET_CODE (PATTERN (insn)) != PARALLEL
@@ -9929,7 +9952,7 @@ sh_fsca_sf2int (void)
 
   return sh_fsca_sf2int_rtx;
 }
-  
+
 /* This function returns a constant rtx that represents pi / 2**15 in
    DFmode.  it's used to scale DFmode angles, in radians, to a
    fixed-point signed 16.16-bit fraction of a full circle, i.e., 2*pi
@@ -9950,7 +9973,7 @@ sh_fsca_df2int (void)
 
   return sh_fsca_df2int_rtx;
 }
-  
+
 /* This function returns a constant rtx that represents 2**15 / pi in
    SFmode.  it's used to scale a fixed-point signed 16.16-bit fraction
    of a full circle back to a SFmode value, i.e., 0x10000 maps to
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
index 259efb0..c249661 100644
--- a/gcc/config/sh/sh.h
+++ b/gcc/config/sh/sh.h
@@ -1303,14 +1303,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
    : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
    : 1)
 
-/* Value is 1 if MODE is a supported vector mode.  */
-#define VECTOR_MODE_SUPPORTED_P(MODE) \
-  ((TARGET_FPU_ANY \
-    && ((MODE) == V2SFmode || (MODE) == V4SFmode || (MODE) == V16SFmode)) \
-   || (TARGET_SHMEDIA \
-       && ((MODE) == V8QImode || (MODE) == V2HImode || (MODE) == V4HImode \
-	   || (MODE) == V2SImode)))
-
 /* Value is 1 if it is a good idea to tie two pseudo registers
    when one has mode MODE1 and one has mode MODE2.
    If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index 9354167..a21a2a4 100644
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -9666,7 +9666,7 @@ mov.l\\t1f,r0\\n\\
 	(match_operand 1 "sh_rep_vec" ""))]
   "TARGET_SHMEDIA && reload_completed
    && GET_MODE (operands[0]) == GET_MODE (operands[1])
-   && VECTOR_MODE_SUPPORTED_P (GET_MODE (operands[0]))
+   && sh_vector_mode_supported_p (GET_MODE (operands[0]))
    && GET_MODE_SIZE (GET_MODE (operands[0])) == 8
    && (XVECEXP (operands[1], 0, 0) != const0_rtx
        || XVECEXP (operands[1], 0, 1) != const0_rtx)
@@ -9710,7 +9710,7 @@ mov.l\\t1f,r0\\n\\
 	(match_operand 1 "sh_const_vec" ""))]
   "TARGET_SHMEDIA && reload_completed
    && GET_MODE (operands[0]) == GET_MODE (operands[1])
-   && VECTOR_MODE_SUPPORTED_P (GET_MODE (operands[0]))
+   && sh_vector_mode_supported_p (GET_MODE (operands[0]))
    && operands[1] != CONST0_RTX (GET_MODE (operands[1]))"
   [(set (match_dup 0) (match_dup 1))]
   "
@@ -10946,4 +10946,3 @@ mov.l\\t1f,r0\\n\\
   return \"\";
 }"
   [(set_attr "type" "other")])
-