config.gcc (sh*-*-*): Define SUPPORT_* macros to 1.

	* config.gcc (sh*-*-*): Define SUPPORT_* macros to 1.
	* config/sh/sh.h: Update mask names throughout.
	(target_flags, ISIZE_BIT, DALIGN_BIT, SH1_BIT, SH2_BIT, SH3_BIT)
	(SH_E_BIT, HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, SH4A_BIT, FMOVD_BIT)
	(SH5_BIT, SPACE_BIT, BIGTABLE_BIT, RELAX_BIT, USERMODE_BIT)
	(HITACHI_BIT, NOMACSAVE_BIT, PREFERGOT_BIT, PADSTRUCT_BIT)
	(LITTLE_ENDIAN_BIT, IEEE_BIT, SAVE_ALL_TR_BIT, HARD_SH2A_BIT)
	(HARD_SH2A_DOUBLE_BIT, INDEXED_ADDRESS_BIT, PT_FIXED_BIT)
	(INVALID_SYMBOLS_BIT, ADJUST_UNROLL_BIT, TARGET_DUMPISIZE)
	(TARGET_ALIGN_DOUBLE, TARGET_SH1, TARGET_SH2, TARGET_SH3)
	(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH5, TARGET_FMOVD)
	(TARGET_IEEE, TARGET_SMALLCODE, TARGET_BIGTABLE, TARGET_RELAX)
	(TARGET_HITACHI, TARGET_NOMACSAVE, TARGET_PADSTRUCT)
	(TARGET_LITTLE_ENDIAN, TARGET_USERMODE, TARGET_PREFERGOT)
	(TARGET_SAVE_ALL_TARGET_REGS, TARGET_ALLOW_INDEXED_ADDRESS)
	(TARGET_PT_FIXED, TARGET_INVALID_SYMBOLS, TARGET_ADJUST_UNROLL)
	(TARGET_SWITCH_SH1, TARGET_SWITCH_SH2, TARGET_SWITCH_SH2E)
	(TARGET_SWITCH_SH2A, TARGET_SWITCH_SH2A_SINGLE_ONLY)
	(TARGET_SWITCH_SH2A_SINGLE, TARGET_SWITCH_SH2A_NOFPU)
	(TARGET_SWITCH_SH3, TARGET_SWITCH_SH3E, TARGET_SWITCH_SH4_SINGLE_ONLY)
	(TARGET_SWITCH_SH4_SINGLE, TARGET_SWITCH_SH4_NOFPU, TARGET_SWITCH_SH4)
	(TARGET_SWITCH_SH4A, TARGET_SWITCH_SH4A_SINGLE_ONLY)
	(TARGET_SWITCH_SH4A_SINGLE, TARGET_SWITCH_SH4A_NOFPU)
	(TARGET_SWITCH_SH4AL, TARGET_SWITCH_SH5_64MEDIA)
	(TARGET_SWITCH_SH5_64MEDIA_NOFPU, TARGET_SWITCHES_SH5_32MEDIA)
	(TARGET_SWITCHES_SH5_32MEDIA_NOFPU, TARGET_SWITCH_SH5_32_ANY_EXTRA)
	(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA, TARGET_SWITCHES)
	(SUBTARGET_SWITCHES): Delete.
	(TARGET_SH2E, TARGET_SH2A, TARGET_SH2A_SINGLE, TARGET_SH2A_DOUBLE)
	(TARGET_SH3E, TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARVARD)
	(TARGET_FPU_DOUBLE, TARGET_SH4A_ARCH, TARGET_SHMEDIA32)
	(TARGET_SHMEDIA64): Redefine using other TARGET_* macros.
	(TARGET_SH4): Undefine options.h definition and check MASK_SH1 as well.
	(SUPPORT_SH1, SUPPORT_SH2E, SUPPORT_SH4, SUPPORT_SH4_SINGLE)
	(SUPPORT_SH2A, SUPPORT_SH2A_SINGLE): Make numeric.
	(SUPPORT_SH2): Define to 1 if SUPPORT_SH1.
	(SUPPORT_SH3): Likewise SUPPORT_SH2.
	(SUPPORT_SH4_NOFPU): Likewise SUPPORT_SH3.
	(SUPPORT_SH4A_NOFPU, SUPPORT_SH4AL, SUPPORT_SH2A_NOFPU): Likewise
	SUPPORT_SH4_NOFPU.
	(SUPPORT_SH3E): Likewise SUPPORT_SH2E.
	(SUPPORT_SH4_SINGLE_ONLY, SUPPORT_SH4A_SINGLE_ONLY)
	(SUPPORT_SH2A_SINGLE_ONLY): Likewise SUPPORT_SH3E.
	(SUPPORT_SH4A): Likewise SUPPORT_SH4.
	(SUPPORT_SH4A_SINGLE): Likewise SUPPORT_SH4_SINGLE.
	(SUPPORT_SH5_32MEDIA): Likewise SUPPORT_SH5_COMPACT.
	(SUPPORT_SH5_32MEDIA_NOFPU): Likewise SUPPORT_SH5_COMPACT_NOFPU.
	(SUPPORT_ANY_SH5_32MEDIA, SUPPORT_ANY_SH5_64MEDIA)
	(SUPPORT_ANY_SH5): New macros.
	(TARGET_NONE): Replace with...
	(MASK_ARCH): ...this new macro.
	* config/sh/elf.h: Update mask names
	* config/sh/linux.h: Likewise.
	* config/sh/little.h: Likewise.
	* config/sh/netbsd-elf.h: Likewise.
	* config/sh/symbian-pre.h: Likewise.
	* config/sh/sh.c (sh_handle_option): New function.
	(TARGET_DEFAULT_TARGET_FLAGS, TARGET_HANDLE_OPTION): Override defaults.
	(calc_live_regs): Use MASK_FPU_SINGLE instead of FPU_SINGLE_BIT.
	(sh_target_switches, target_switches): Delete.
	(sh_pch_valid_p): Check for specific differences in the target_flags
	settings.
	(sh_init_cumulative_args): Use MASK_HITACHI instead of HITACHI_BIT.
	* config/sh/sh.opt: New file.

From-SVN: r99916

8 files changed, 452 insertions, 467 deletions

diff --git a/gcc/config/sh/elf.h b/gcc/config/sh/elf.h
index 0dab7d8..52d0727 100644
--- a/gcc/config/sh/elf.h
+++ b/gcc/config/sh/elf.h
@@ -61,7 +61,7 @@ Boston, MA 02111-1307, USA.  */
 #undef LINK_SPEC
 #define LINK_SPEC SH_LINK_SPEC
 #undef LINK_EMUL_PREFIX
-#if TARGET_ENDIAN_DEFAULT == LITTLE_ENDIAN_BIT
+#if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
 #define LINK_EMUL_PREFIX "sh%{!mb:l}elf"
 #else
 #define LINK_EMUL_PREFIX "sh%{ml:l}elf"
diff --git a/gcc/config/sh/linux.h b/gcc/config/sh/linux.h
index 013bf49..fe48d0c 100644
--- a/gcc/config/sh/linux.h
+++ b/gcc/config/sh/linux.h
@@ -48,7 +48,7 @@ Boston, MA 02111-1307, USA.  */
 
 #undef TARGET_DEFAULT
 #define TARGET_DEFAULT \
-  (TARGET_CPU_DEFAULT | USERMODE_BIT | TARGET_ENDIAN_DEFAULT \
+  (TARGET_CPU_DEFAULT | MASK_USERMODE | TARGET_ENDIAN_DEFAULT \
    | TARGET_OPT_DEFAULT)
 
 #define TARGET_ASM_FILE_END file_end_indicate_exec_stack
diff --git a/gcc/config/sh/little.h b/gcc/config/sh/little.h
index 98c2bc2..c0ccbd7 100644
--- a/gcc/config/sh/little.h
+++ b/gcc/config/sh/little.h
@@ -19,4 +19,4 @@ along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
-#define TARGET_ENDIAN_DEFAULT LITTLE_ENDIAN_BIT
+#define TARGET_ENDIAN_DEFAULT MASK_LITTLE_ENDIAN
diff --git a/gcc/config/sh/netbsd-elf.h b/gcc/config/sh/netbsd-elf.h
index c640ba0..92d7ae1 100644
--- a/gcc/config/sh/netbsd-elf.h
+++ b/gcc/config/sh/netbsd-elf.h
@@ -20,21 +20,21 @@ the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
 /* Run-time Target Specification.  */
-#if TARGET_ENDIAN_DEFAULT == LITTLE_ENDIAN_BIT
+#if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
 #define TARGET_VERSION_ENDIAN "le"
 #else
 #define TARGET_VERSION_ENDIAN ""
 #endif
 
-#if TARGET_CPU_DEFAULT & SH5_BIT
-#if TARGET_CPU_DEFAULT & SH_E_BIT
+#if TARGET_CPU_DEFAULT & MASK_SH5
+#if TARGET_CPU_DEFAULT & MASK_SH_E
 #define TARGET_VERSION_CPU "sh5"
 #else
 #define TARGET_VERSION_CPU "sh64"
-#endif /* SH_E_BIT */
+#endif /* MASK_SH_E */
 #else
 #define TARGET_VERSION_CPU "sh"
-#endif /* SH5_BIT */
+#endif /* MASK_SH5 */
 
 #undef TARGET_VERSION
 #define TARGET_VERSION	fprintf (stderr, " (NetBSD/%s%s ELF)",		\
@@ -80,7 +80,7 @@ Boston, MA 02111-1307, USA.  */
 
 #undef TARGET_DEFAULT
 #define TARGET_DEFAULT \
-  (TARGET_CPU_DEFAULT | USERMODE_BIT | TARGET_ENDIAN_DEFAULT)
+  (TARGET_CPU_DEFAULT | MASK_USERMODE | TARGET_ENDIAN_DEFAULT)
 
 /* Define because we use the label and we do not need them.  */
 #define NO_PROFILE_COUNTERS 1
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index 41f6e72..a0b7862 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -198,6 +198,7 @@ int assembler_dialect;
 
 static bool shmedia_space_reserved_for_target_registers;
 
+static bool sh_handle_option (size_t, const char *, int);
 static void split_branches (rtx);
 static int branch_dest (rtx);
 static void force_into (rtx, rtx);
@@ -325,6 +326,11 @@ static int hard_regs_intersect_p (HARD_REG_SET *, HARD_REG_SET *);
 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
 
+#undef TARGET_DEFAULT_TARGET_FLAGS
+#define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
+#undef TARGET_HANDLE_OPTION
+#define TARGET_HANDLE_OPTION sh_handle_option
+
 #undef TARGET_INSERT_ATTRIBUTES
 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
 
@@ -491,6 +497,112 @@ static int hard_regs_intersect_p (HARD_REG_SET *, HARD_REG_SET *);
 
 struct gcc_target targetm = TARGET_INITIALIZER;
 
+/* Implement TARGET_HANDLE_OPTION.  */
+
+static bool
+sh_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED,
+		  int value ATTRIBUTE_UNUSED)
+{
+  switch (code)
+    {
+    case OPT_m1:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH1;
+      return true;
+
+    case OPT_m2:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2;
+      return true;
+
+    case OPT_m2a:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A;
+      return true;
+
+    case OPT_m2a_nofpu:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_NOFPU;
+      return true;
+
+    case OPT_m2a_single:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE;
+      return true;
+
+    case OPT_m2a_single_only:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2A_SINGLE_ONLY;
+      return true;
+
+    case OPT_m2e:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH2E;
+      return true;
+
+    case OPT_m3:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3;
+      return true;
+
+    case OPT_m3e:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH3E;
+      return true;
+
+    case OPT_m4:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4;
+      return true;
+
+    case OPT_m4_nofpu:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_NOFPU;
+      return true;
+
+    case OPT_m4_single:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE;
+      return true;
+
+    case OPT_m4_single_only:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4_SINGLE_ONLY;
+      return true;
+
+    case OPT_m4a:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A;
+      return true;
+
+    case OPT_m4a_nofpu:
+    case OPT_m4al:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_NOFPU;
+      return true;
+
+    case OPT_m4a_single:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE;
+      return true;
+
+    case OPT_m4a_single_only:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE_ONLY;
+      return true;
+
+    case OPT_m5_32media:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA;
+      return true;
+
+    case OPT_m5_32media_nofpu:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA_NOFPU;
+      return true;
+
+    case OPT_m5_64media:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA;
+      return true;
+
+    case OPT_m5_64media_nofpu:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA_NOFPU;
+      return true;
+
+    case OPT_m5_compact:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT;
+      return true;
+
+    case OPT_m5_compact_nofpu:
+      target_flags = (target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT_NOFPU;
+      return true;
+
+    default:
+      return true;
+    }
+}
+
 /* Print the operand address in x to the stream.  */
 
 void
@@ -5236,7 +5348,7 @@ calc_live_regs (HARD_REG_SET *live_regs_mask)
   CLEAR_HARD_REG_SET (*live_regs_mask);
   if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && interrupt_handler
       && regs_ever_live[FPSCR_REG])
-    target_flags &= ~FPU_SINGLE_BIT;
+    target_flags &= ~MASK_FPU_SINGLE;
   /* If we can save a lot of saves by switching to double mode, do that.  */
   else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && TARGET_FPU_SINGLE)
     for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
@@ -5245,7 +5357,7 @@ calc_live_regs (HARD_REG_SET *live_regs_mask)
 	      || (interrupt_handler && ! pragma_trapa))
 	  && ++count > 2)
 	{
-	  target_flags &= ~FPU_SINGLE_BIT;
+	  target_flags &= ~MASK_FPU_SINGLE;
 	  break;
 	}
   /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
@@ -5327,7 +5439,7 @@ calc_live_regs (HARD_REG_SET *live_regs_mask)
 	      else if (XD_REGISTER_P (reg))
 		{
 		  /* Must switch to double mode to access these registers.  */
-		  target_flags &= ~FPU_SINGLE_BIT;
+		  target_flags &= ~MASK_FPU_SINGLE;
 		}
 	    }
 	}
@@ -7403,17 +7515,7 @@ sh_cfun_interrupt_handler_p (void)
 	  != NULL_TREE);
 }
 
-/* ??? target_switches in toplev.c is static, hence we have to duplicate it.  */
-static const struct
-{
-  const char *const name;
-  const int value;
-  const char *const description;
-}
-sh_target_switches[] = TARGET_SWITCHES;
-#define target_switches sh_target_switches
-
-/* Like default_pch_valid_p, but take flag_mask into account.  */
+/* Like default_pch_valid_p, but only check certain target_flags.  */
 const char *
 sh_pch_valid_p (const void *data_p, size_t len)
 {
@@ -7433,9 +7535,6 @@ sh_pch_valid_p (const void *data_p, size_t len)
   const char *flag_that_differs = NULL;
   size_t i;
   int old_flags;
-  int flag_mask
-    = (SH1_BIT | SH2_BIT | SH3_BIT | SH_E_BIT | HARD_SH4_BIT | FPU_SINGLE_BIT
-       | SH4_BIT | HITACHI_BIT | LITTLE_ENDIAN_BIT);
 
   /* -fpic and -fpie also usually make a PCH invalid.  */
   if (data[0] != flag_pic)
@@ -7446,24 +7545,15 @@ sh_pch_valid_p (const void *data_p, size_t len)
 
   /* Check target_flags.  */
   memcpy (&old_flags, data, sizeof (target_flags));
-  if (((old_flags ^ target_flags) & flag_mask) != 0)
-    {
-      for (i = 0; i < ARRAY_SIZE (target_switches); i++)
-	{
-	  int bits;
+  if ((old_flags ^ target_flags) & (MASK_SH1 | MASK_SH2 | MASK_SH3
+				    | MASK_SH_E | MASK_HARD_SH4
+				    | MASK_FPU_SINGLE | MASK_SH4))
+    return _("created and used with different architectures / ABIs");
+  if ((old_flags ^ target_flags) & MASK_HITACHI)
+    return _("created and used with different ABIs");
+  if ((old_flags ^ target_flags) & MASK_LITTLE_ENDIAN)
+    return _("created and used with different endianness");
 
-	  bits = target_switches[i].value;
-	  if (bits < 0)
-	    bits = -bits;
-	  bits &= flag_mask;
-	  if ((target_flags & bits) != (old_flags & bits))
-	    {
-	      flag_that_differs = target_switches[i].name;
-	      goto make_message;
-	    }
-	}
-      gcc_unreachable ();
-    }
   data += sizeof (target_flags);
   len -= sizeof (target_flags);
 
@@ -10649,7 +10739,7 @@ sh_init_cumulative_args (CUMULATIVE_ARGS *  pcum,
 	     the TYPE or the FNDECL available so we synthesize the
 	     contents of that function as best we can.  */
 	  pcum->force_mem =
-	    (TARGET_DEFAULT & HITACHI_BIT)
+	    (TARGET_DEFAULT & MASK_HITACHI)
 	    && (mode == BLKmode
 		|| (GET_MODE_SIZE (mode) > 4
 		    && !(mode == DFmode
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
index 32ad39c..92d8ce0 100644
--- a/gcc/config/sh/sh.h
+++ b/gcc/config/sh/sh.h
@@ -148,108 +148,49 @@ do { \
 	SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno);	\
 } while (0)
 
-/* ??? Need to write documentation for all SH options and add it to the
-   invoke.texi file.  */
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-extern int target_flags;
-#define ISIZE_BIT      	(1<<1)
-#define DALIGN_BIT     	(1<<6)
-#define SH1_BIT	       	(1<<8)
-#define SH2_BIT	       	(1<<9)
-#define SH3_BIT	       	(1<<10)
-#define SH_E_BIT	(1<<11)
-#define HARD_SH4_BIT	(1<<5)
-#define FPU_SINGLE_BIT	(1<<7)
-#define SH4_BIT	       	(1<<12)
-#define SH4A_BIT	(1<<3)
-#define FMOVD_BIT	(1<<4)
-#define SH5_BIT		(1<<0)
-#define SPACE_BIT 	(1<<13)
-#define BIGTABLE_BIT  	(1<<14)
-#define RELAX_BIT	(1<<15)
-#define USERMODE_BIT	(1<<16)
-#define HITACHI_BIT     (1<<22)
-#define NOMACSAVE_BIT   (1<<23)
-#define PREFERGOT_BIT	(1<<24)
-#define PADSTRUCT_BIT  (1<<28)
-#define LITTLE_ENDIAN_BIT (1<<29)
-#define IEEE_BIT (1<<30)
-#define SAVE_ALL_TR_BIT (1<<2)
-#define HARD_SH2A_BIT	(1<<17)
-#define HARD_SH2A_DOUBLE_BIT	(1<<18)
-#define INDEXED_ADDRESS_BIT (1<<19)
-#define PT_FIXED_BIT	(1<<21)
-#define INVALID_SYMBOLS_BIT (1<<25)
-#define ADJUST_UNROLL_BIT (1<<20)
-
 /* Nonzero if this is an ELF target - compile time only */
 #define TARGET_ELF 0
 
-/* Nonzero if we should dump out instruction size info.  */
-#define TARGET_DUMPISIZE  (target_flags & ISIZE_BIT)
-
-/* Nonzero to align doubles on 64 bit boundaries.  */
-#define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
-
-/* Nonzero if we should generate code using type 1 insns.  */
-#define TARGET_SH1 (target_flags & SH1_BIT)
-
-/* Nonzero if we should generate code using type 2 insns.  */
-#define TARGET_SH2 (target_flags & SH2_BIT)
-
 /* Nonzero if we should generate code using type 2E insns.  */
-#define TARGET_SH2E ((target_flags & SH_E_BIT) && TARGET_SH2)
+#define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
 
 /* Nonzero if we should generate code using type 2A insns.  */
-#define TARGET_SH2A (target_flags & HARD_SH2A_BIT)
+#define TARGET_SH2A TARGET_HARD_SH2A
 /* Nonzero if we should generate code using type 2A SF insns.  */
-#define TARGET_SH2A_SINGLE ((target_flags & HARD_SH2A_BIT) && TARGET_SH2E)
+#define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
 /* Nonzero if we should generate code using type 2A DF insns.  */
-#define TARGET_SH2A_DOUBLE ((target_flags & HARD_SH2A_DOUBLE_BIT) && TARGET_SH2A)
-
-/* Nonzero if we should generate code using type 3 insns.  */
-#define TARGET_SH3 (target_flags & SH3_BIT)
+#define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
 
 /* Nonzero if we should generate code using type 3E insns.  */
-#define TARGET_SH3E ((target_flags & SH_E_BIT) && TARGET_SH3)
+#define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
 
 /* Nonzero if the cache line size is 32.  */
-#define TARGET_CACHE32 (target_flags & HARD_SH4_BIT || TARGET_SH5)
+#define TARGET_CACHE32 (TARGET_HARD_SH4 || TARGET_SH5)
 
 /* Nonzero if we schedule for a superscalar implementation.  */
-#define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT)
+#define TARGET_SUPERSCALAR TARGET_HARD_SH4
 
 /* Nonzero if the target has separate instruction and data caches.  */
-#define TARGET_HARVARD (target_flags & HARD_SH4_BIT || TARGET_SH5)
-
-/* Nonzero if compiling for SH4 hardware (to be used for insn costs etc.)  */
-#define TARGET_HARD_SH4 (target_flags & HARD_SH4_BIT)
-
-/* Nonzero if the default precision of th FPU is single */
-#define TARGET_FPU_SINGLE (target_flags & FPU_SINGLE_BIT)
+#define TARGET_HARVARD (TARGET_HARD_SH4 || TARGET_SH5)
 
 /* Nonzero if a double-precision FPU is available.  */
-#define TARGET_FPU_DOUBLE ((target_flags & SH4_BIT) || TARGET_SH2A_DOUBLE)
+#define TARGET_FPU_DOUBLE (TARGET_SH4 || TARGET_SH2A_DOUBLE)
 
 /* Nonzero if an FPU is available.  */
 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
 
 /* Nonzero if we should generate code using type 4 insns.  */
-#define TARGET_SH4 ((target_flags & SH4_BIT) && (target_flags & SH1_BIT))
+#undef TARGET_SH4
+#define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)
 
 /* Nonzero if we're generating code for the common subset of
    instructions present on both SH4a and SH4al-dsp.  */
-#define TARGET_SH4A_ARCH (target_flags & SH4A_BIT)
+#define TARGET_SH4A_ARCH TARGET_SH4A
 
 /* Nonzero if we're generating code for SH4a, unless the use of the
    FPU is disabled (which makes it compatible with SH4al-dsp).  */
 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
 
-/* Nonzero if we should generate code for a SH5 CPU (either ISA).  */
-#define TARGET_SH5 (target_flags & SH5_BIT)
-
 /* Nonzero if we should generate code using the SHcompact instruction
    set and 32-bit ABI.  */
 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
@@ -260,55 +201,14 @@ extern int target_flags;
 
 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
    ABI.  */
-#define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 \
-			  && (target_flags & SH_E_BIT))
+#define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E)
 
 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
    ABI.  */
-#define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 \
- 			  && ! (target_flags & SH_E_BIT))
+#define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E)
 
 /* Nonzero if we should generate code using SHmedia FPU instructions.  */
 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
-/* Nonzero if we should generate fmovd.  */
-#define TARGET_FMOVD (target_flags & FMOVD_BIT)
-
-/* Nonzero if we respect NANs.  */
-#define TARGET_IEEE (target_flags & IEEE_BIT)
-
-/* Nonzero if we should generate smaller code rather than faster code.  */
-#define TARGET_SMALLCODE   (target_flags & SPACE_BIT)
-
-/* Nonzero to use long jump tables.  */
-#define TARGET_BIGTABLE     (target_flags & BIGTABLE_BIT)
-
-/* Nonzero to generate pseudo-ops needed by the assembler and linker
-   to do function call relaxing.  */
-#define TARGET_RELAX (target_flags & RELAX_BIT)
-
-/* Nonzero if using Renesas's calling convention.  */
-#define TARGET_HITACHI 		(target_flags & HITACHI_BIT)
-
-/* Nonzero if not saving macl/mach when using -mhitachi */
-#define TARGET_NOMACSAVE	(target_flags & NOMACSAVE_BIT)
-
-/* Nonzero if padding structures to a multiple of 4 bytes.  This is
-   incompatible with Renesas's compiler, and gives unusual structure layouts
-   which confuse programmers.
-   ??? This option is not useful, but is retained in case there are people
-   who are still relying on it.  It may be deleted in the future.  */
-#define TARGET_PADSTRUCT       (target_flags & PADSTRUCT_BIT)
-
-/* Nonzero if generating code for a little endian SH.  */
-#define TARGET_LITTLE_ENDIAN     (target_flags & LITTLE_ENDIAN_BIT)
-
-/* Nonzero if we should do everything in userland.  */
-#define TARGET_USERMODE		(target_flags & USERMODE_BIT)
-
-/* Nonzero if we should prefer @GOT calls when generating PIC.  */
-#define TARGET_PREFERGOT	(target_flags & PREFERGOT_BIT)
-
-#define TARGET_SAVE_ALL_TARGET_REGS (target_flags & SAVE_ALL_TR_BIT)
 
 /* This is not used by the SH2E calling convention  */
 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
@@ -317,12 +217,12 @@ extern int target_flags;
 
 #ifndef TARGET_CPU_DEFAULT
 #define TARGET_CPU_DEFAULT SELECT_SH1
-#define SUPPORT_SH1
-#define SUPPORT_SH2E
-#define SUPPORT_SH4
-#define SUPPORT_SH4_SINGLE
-#define SUPPORT_SH2A
-#define SUPPORT_SH2A_SINGLE
+#define SUPPORT_SH1 1
+#define SUPPORT_SH2E 1
+#define SUPPORT_SH4 1
+#define SUPPORT_SH4_SINGLE 1
+#define SUPPORT_SH2A 1
+#define SUPPORT_SH2A_SINGLE 1
 #endif
 
 #define TARGET_DIVIDE_INV \
@@ -339,307 +239,88 @@ extern int target_flags;
 #define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL)
 #define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2)
 
-/* Target macros pertaining to SHmedia architecture bugs.  */
-#define TARGET_ALLOW_INDEXED_ADDRESS (target_flags & INDEXED_ADDRESS_BIT)
-#define TARGET_PT_FIXED (target_flags & PT_FIXED_BIT)
-#define TARGET_INVALID_SYMBOLS (target_flags & INVALID_SYMBOLS_BIT)
-
-#define TARGET_ADJUST_UNROLL (target_flags & ADJUST_UNROLL_BIT)
-
-#define SELECT_SH1               (SH1_BIT)
-#define SELECT_SH2               (SH2_BIT | SELECT_SH1)
-#define SELECT_SH2E              (SH_E_BIT | SH2_BIT | SH1_BIT | FPU_SINGLE_BIT)
-#define SELECT_SH2A              (SH_E_BIT | HARD_SH2A_BIT | HARD_SH2A_DOUBLE_BIT | SH2_BIT | SH1_BIT)
-#define SELECT_SH2A_NOFPU        (HARD_SH2A_BIT | SH2_BIT | SH1_BIT)
-#define SELECT_SH2A_SINGLE_ONLY  (SH_E_BIT | HARD_SH2A_BIT | SH2_BIT | SH1_BIT | FPU_SINGLE_BIT)
-#define SELECT_SH2A_SINGLE       (SH_E_BIT | HARD_SH2A_BIT | FPU_SINGLE_BIT \
-				  | HARD_SH2A_DOUBLE_BIT | SH2_BIT | SH1_BIT)
-#define SELECT_SH3               (SH3_BIT | SELECT_SH2)
-#define SELECT_SH3E              (SH_E_BIT | FPU_SINGLE_BIT | SELECT_SH3)
-#define SELECT_SH4_NOFPU         (HARD_SH4_BIT | SELECT_SH3)
-#define SELECT_SH4_SINGLE_ONLY   (HARD_SH4_BIT | SELECT_SH3E)
-#define SELECT_SH4               (SH4_BIT | SH_E_BIT | HARD_SH4_BIT | SELECT_SH3)
-#define SELECT_SH4_SINGLE        (FPU_SINGLE_BIT | SELECT_SH4)
-#define SELECT_SH4A_NOFPU        (SH4A_BIT | SELECT_SH4_NOFPU)
-#define SELECT_SH4A_SINGLE_ONLY  (SH4A_BIT | SELECT_SH4_SINGLE_ONLY)
-#define SELECT_SH4A              (SH4A_BIT | SELECT_SH4)
-#define SELECT_SH4A_SINGLE       (SH4A_BIT | SELECT_SH4_SINGLE)
-#define SELECT_SH5_64MEDIA       (SH5_BIT | SH4_BIT)
-#define SELECT_SH5_64MEDIA_NOFPU (SH5_BIT)
-#define SELECT_SH5_32MEDIA       (SH5_BIT | SH4_BIT | SH_E_BIT)
-#define SELECT_SH5_32MEDIA_NOFPU (SH5_BIT | SH_E_BIT)
-#define SELECT_SH5_COMPACT       (SH5_BIT | SH4_BIT | SELECT_SH3E)
-#define SELECT_SH5_COMPACT_NOFPU (SH5_BIT | SELECT_SH3)
-
-/* Disable processor switches for which we have no suitable multilibs.  */
-#ifndef SUPPORT_SH1
-#define TARGET_SWITCH_SH1
-#ifndef SUPPORT_SH2
-#define TARGET_SWITCH_SH2
-#ifndef SUPPORT_SH3
-#define TARGET_SWITCH_SH3
-#ifndef SUPPORT_SH4_NOFPU
-#define TARGET_SWITCH_SH4_NOFPU
-#endif
-#ifndef SUPPORT_SH4A_NOFPU
-#define TARGET_SWITCH_SH4A_NOFPU
-#endif
-#ifndef SUPPORT_SH4AL
-#define TARGET_SWITCH_SH4AL
-#endif
-#ifndef SUPPORT_SH2A_NOFPU
-#define TARGET_SWITCH_SH2A_NOFPU
-#endif
-#endif
-#endif
-#endif
+#define SELECT_SH1               (MASK_SH1)
+#define SELECT_SH2               (MASK_SH2 | SELECT_SH1)
+#define SELECT_SH2E              (MASK_SH_E | MASK_SH2 | MASK_SH1 \
+				  | MASK_FPU_SINGLE)
+#define SELECT_SH2A              (MASK_SH_E | MASK_HARD_SH2A \
+				  | MASK_HARD_SH2A_DOUBLE \
+				  | MASK_SH2 | MASK_SH1)
+#define SELECT_SH2A_NOFPU        (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
+#define SELECT_SH2A_SINGLE_ONLY  (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
+				  | MASK_SH1 | MASK_FPU_SINGLE)
+#define SELECT_SH2A_SINGLE       (MASK_SH_E | MASK_HARD_SH2A \
+				  | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
+				  | MASK_SH2 | MASK_SH1)
+#define SELECT_SH3               (MASK_SH3 | SELECT_SH2)
+#define SELECT_SH3E              (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
+#define SELECT_SH4_NOFPU         (MASK_HARD_SH4 | SELECT_SH3)
+#define SELECT_SH4_SINGLE_ONLY   (MASK_HARD_SH4 | SELECT_SH3E)
+#define SELECT_SH4               (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
+				  | SELECT_SH3)
+#define SELECT_SH4_SINGLE        (MASK_FPU_SINGLE | SELECT_SH4)
+#define SELECT_SH4A_NOFPU        (MASK_SH4A | SELECT_SH4_NOFPU)
+#define SELECT_SH4A_SINGLE_ONLY  (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
+#define SELECT_SH4A              (MASK_SH4A | SELECT_SH4)
+#define SELECT_SH4A_SINGLE       (MASK_SH4A | SELECT_SH4_SINGLE)
+#define SELECT_SH5_64MEDIA       (MASK_SH5 | MASK_SH4)
+#define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
+#define SELECT_SH5_32MEDIA       (MASK_SH5 | MASK_SH4 | MASK_SH_E)
+#define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
+#define SELECT_SH5_COMPACT       (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
+#define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
 
-#ifndef SUPPORT_SH2E
-#define TARGET_SWITCH_SH2E
-#ifndef SUPPORT_SH3E
-#define TARGET_SWITCH_SH3E
-#ifndef SUPPORT_SH4_SINGLE_ONLY
-#define TARGET_SWITCH_SH4_SINGLE_ONLY
-#endif
-#ifndef SUPPORT_SH4A_SINGLE_ONLY
-#define TARGET_SWITCH_SH4A_SINGLE_ONLY
-#endif
-#ifndef SUPPORT_SH2A_SINGLE_ONLY
-#define TARGET_SWITCH_SH2A_SINGLE_ONLY
-#endif
+#if SUPPORT_SH1
+#define SUPPORT_SH2 1
 #endif
+#if SUPPORT_SH2
+#define SUPPORT_SH3 1
 #endif
-
-#ifndef SUPPORT_SH4
-#define TARGET_SWITCH_SH4
-#ifndef SUPPORT_SH4A
-#define TARGET_SWITCH_SH4A
+#if SUPPORT_SH3
+#define SUPPORT_SH4_NOFPU 1
 #endif
+#if SUPPORT_SH4_NOFPU
+#define SUPPORT_SH4A_NOFPU 1
+#define SUPPORT_SH4AL 1
+#define SUPPORT_SH2A_NOFPU 1
 #endif
 
-#ifndef SUPPORT_SH4_SINGLE
-#define TARGET_SWITCH_SH4_SINGLE
-#ifndef SUPPORT_SH4A_SINGLE
-#define TARGET_SWITCH_SH4A_SINGLE
-#endif
+#if SUPPORT_SH2E
+#define SUPPORT_SH3E 1
 #endif
-
-#ifndef SUPPORT_SH2A
-#define TARGET_SWITCH_SH2A
+#if SUPPORT_SH3E
+#define SUPPORT_SH4_SINGLE_ONLY 1
+#define SUPPORT_SH4A_SINGLE_ONLY 1
+#define SUPPORT_SH2A_SINGLE_ONLY 1
 #endif
 
-#ifndef SUPPORT_SH2A_SINGLE
-#define TARGET_SWITCH_SH2A_SINGLE
+#if SUPPORT_SH4
+#define SUPPORT_SH4A 1
 #endif
 
-#ifndef SUPPORT_SH5_64MEDIA
-#define TARGET_SWITCH_SH5_64MEDIA
+#if SUPPORT_SH4_SINGLE
+#define SUPPORT_SH4A_SINGLE 1
 #endif
 
-#ifndef SUPPORT_SH5_64MEDIA_NOFPU
-#define TARGET_SWITCH_SH5_64MEDIA_NOFPU
+#if SUPPORT_SH5_COMPAT
+#define SUPPORT_SH5_32MEDIA 1
 #endif
 
-#if !defined(SUPPORT_SH5_32MEDIA) && !defined (SUPPORT_SH5_COMPACT)
-#define TARGET_SWITCHES_SH5_32MEDIA
+#if SUPPORT_SH5_COMPACT_NOFPU
+#define SUPPORT_SH5_32MEDIA_NOFPU 1
 #endif
 
-#if !defined(SUPPORT_SH5_32MEDIA_NOFPU) && !defined (SUPPORT_SH5_COMPACT_NOFPU)
-#define TARGET_SWITCHES_SH5_32MEDIA_NOFPU
-#endif
-
-#if defined(TARGET_SWITCHES_SH5_32MEDIA) && defined(TARGET_SWITCHES_SH5_32MEDIA_NOFPU)
-#define TARGET_SWITCH_SH5_32_ANY_EXTRA
-#endif
-
-#if defined(TARGET_SWITCH_SH5_32_ANY_EXTRA) && !defined(SUPPORT_SH5_64MEDIA) && !defined(SUPPORT_SH5_64MEDIA_NOFPU)
-#define TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA
-#endif
+#define SUPPORT_ANY_SH5_32MEDIA \
+  (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU)
+#define SUPPORT_ANY_SH5_64MEDIA \
+  (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU)
+#define SUPPORT_ANY_SH5 \
+  (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA)
 
 /* Reset all target-selection flags.  */
-#define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH_E_BIT | SH4_BIT \
-		      | HARD_SH2A_BIT | HARD_SH2A_DOUBLE_BIT \
-		      | SH4A_BIT | HARD_SH4_BIT | FPU_SINGLE_BIT | SH5_BIT)
-
-#ifndef TARGET_SWITCH_SH1
-#define TARGET_SWITCH_SH1 \
-  {"1",		TARGET_NONE, "" }, \
-  {"1",		SELECT_SH1, "Generate SH1 code" },
-#endif
-#ifndef TARGET_SWITCH_SH2
-#define TARGET_SWITCH_SH2 \
-  {"2",		TARGET_NONE, "" }, \
-  {"2",		SELECT_SH2, "Generate SH2 code" },
-#endif
-#ifndef TARGET_SWITCH_SH2E
-#define TARGET_SWITCH_SH2E \
-  {"2e",	TARGET_NONE, "" }, \
-  {"2e",	SELECT_SH2E, "Generate SH2e code" },
-#endif
-#ifndef TARGET_SWITCH_SH2A
-#define TARGET_SWITCH_SH2A \
-  {"2a",	TARGET_NONE, "" }, \
-  {"2a",	SELECT_SH2A, "Generate SH2a code" },
-#endif
-#ifndef TARGET_SWITCH_SH2A_SINGLE_ONLY
-#define TARGET_SWITCH_SH2A_SINGLE_ONLY \
-  {"2a-single-only", TARGET_NONE, "" },	\
-  {"2a-single-only", SELECT_SH2A_SINGLE_ONLY, "Generate only single-precision SH2a code" },
-#endif
-#ifndef TARGET_SWITCH_SH2A_SINGLE
-#define TARGET_SWITCH_SH2A_SINGLE \
-  {"2a-single", TARGET_NONE, "" },	\
-  {"2a-single", SELECT_SH2A_SINGLE, "Generate default single-precision SH2a code" },
-#endif
-#ifndef TARGET_SWITCH_SH2A_NOFPU
-#define TARGET_SWITCH_SH2A_NOFPU \
-  {"2a-nofpu",  TARGET_NONE, "" },	\
-  {"2a-nofpu",  SELECT_SH2A_NOFPU, "Generate SH2a FPU-less code" },
-#endif
-#ifndef TARGET_SWITCH_SH3
-#define TARGET_SWITCH_SH3 \
-  {"3",		TARGET_NONE, "" }, \
-  {"3",		SELECT_SH3, "Generate SH3 code" },
-#endif
-#ifndef TARGET_SWITCH_SH3E
-#define TARGET_SWITCH_SH3E \
-  {"3e",	TARGET_NONE, "" }, \
-  {"3e",	SELECT_SH3E, "Generate SH3e code" },
-#endif
-#ifndef TARGET_SWITCH_SH4_SINGLE_ONLY
-#define TARGET_SWITCH_SH4_SINGLE_ONLY \
-  {"4-single-only",	TARGET_NONE, "" }, \
-  {"4-single-only",	SELECT_SH4_SINGLE_ONLY, "Generate only single-precision SH4 code" },
-#endif
-#ifndef TARGET_SWITCH_SH4_SINGLE
-#define TARGET_SWITCH_SH4_SINGLE \
-  {"4-single",	TARGET_NONE, "" }, \
-  {"4-single",	SELECT_SH4_SINGLE, "Generate default single-precision SH4 code" },
-#endif
-#ifndef TARGET_SWITCH_SH4_NOFPU
-#define TARGET_SWITCH_SH4_NOFPU \
-  {"4-nofpu",	TARGET_NONE, "" }, \
-  {"4-nofpu",	SELECT_SH4_NOFPU, "Generate SH4 FPU-less code" },
-#endif
-#ifndef TARGET_SWITCH_SH4
-#define TARGET_SWITCH_SH4 \
-  {"4",		TARGET_NONE, "" }, \
-  {"4",		SELECT_SH4, "Generate SH4 code" },
-#endif
-#ifndef TARGET_SWITCH_SH4A
-#define TARGET_SWITCH_SH4A \
-  {"4a",	TARGET_NONE, "" }, \
-  {"4a",	SELECT_SH4A, "Generate SH4a code" },
-#endif
-#ifndef TARGET_SWITCH_SH4A_SINGLE_ONLY
-#define TARGET_SWITCH_SH4A_SINGLE_ONLY \
-  {"4a-single-only",	TARGET_NONE, "" },	\
-  {"4a-single-only",	SELECT_SH4A_SINGLE_ONLY, "Generate only single-precision SH4a code" },
-#endif
-#ifndef TARGET_SWITCH_SH4A_SINGLE
-#define TARGET_SWITCH_SH4A_SINGLE \
-  {"4a-single",	TARGET_NONE, "" },\
-  {"4a-single",	SELECT_SH4A_SINGLE, "Generate default single-precision SH4a code" },
-#endif
-#ifndef TARGET_SWITCH_SH4A_NOFPU
-#define TARGET_SWITCH_SH4A_NOFPU \
-  {"4a-nofpu",	TARGET_NONE, "" },\
-  {"4a-nofpu",	SELECT_SH4A_NOFPU, "Generate SH4a FPU-less code" },
-#endif
-#ifndef TARGET_SWITCH_SH4AL
-#define TARGET_SWITCH_SH4AL \
-  {"4al",	TARGET_NONE, "" },\
-  {"4al",	SELECT_SH4A_NOFPU, "Generate SH4al-dsp code" },
-#endif
-#ifndef TARGET_SWITCH_SH5_64MEDIA
-#define TARGET_SWITCH_SH5_64MEDIA \
-  {"5-64media",	TARGET_NONE, "" },		\
-  {"5-64media", SELECT_SH5_64MEDIA, "Generate 64-bit SHmedia code" },
-#endif
-#ifndef TARGET_SWITCH_SH5_64MEDIA_NOFPU
-#define TARGET_SWITCH_SH5_64MEDIA_NOFPU \
-  {"5-64media-nofpu", TARGET_NONE, "" },	\
-  {"5-64media-nofpu", SELECT_SH5_64MEDIA_NOFPU, "Generate 64-bit FPU-less SHmedia code" },
-#endif
-#ifndef TARGET_SWITCHES_SH5_32MEDIA
-#define TARGET_SWITCHES_SH5_32MEDIA \
-  {"5-32media",	TARGET_NONE, "" },		\
-  {"5-32media", SELECT_SH5_32MEDIA, "Generate 32-bit SHmedia code" }, \
-  {"5-compact",	TARGET_NONE, "" },		\
-  {"5-compact",	SELECT_SH5_COMPACT, "Generate SHcompact code" },
-#endif
-#ifndef TARGET_SWITCHES_SH5_32MEDIA_NOFPU
-#define TARGET_SWITCHES_SH5_32MEDIA_NOFPU \
-  {"5-32media-nofpu", TARGET_NONE, "" },	\
-  {"5-32media-nofpu", SELECT_SH5_32MEDIA_NOFPU, "Generate 32-bit FPU-less SHmedia code" }, \
-  {"5-compact-nofpu", TARGET_NONE, "" },	\
-  {"5-compact-nofpu", SELECT_SH5_COMPACT_NOFPU, "Generate FPU-less SHcompact code" },
-#endif
-
-#ifndef TARGET_SWITCH_SH5_32_ANY_EXTRA
-#define TARGET_SWITCH_SH5_32_ANY_EXTRA \
-  {"indexed-addressing", INDEXED_ADDRESS_BIT, "Enable the use of the indexed addressing mode for SHmedia32/SHcompact"}, \
-  {"no-indexed-addressing", -INDEXED_ADDRESS_BIT, "Disable the use of the indexed addressing mode for SHmedia32/SHcompact"},
-#endif
-
-#ifndef TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA
-#define TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA \
-  {"pt-fixed",	PT_FIXED_BIT, "Assume pt* instructions won't trap"}, \
-  {"no-pt-fixed", -PT_FIXED_BIT, "Assume pt* instructions may trap"}, \
-  {"invalid-symbols",INVALID_SYMBOLS_BIT, "Assume symbols might be invalid"}, \
-  {"no-invalid-symbols",-INVALID_SYMBOLS_BIT, "Assume symbols won't be invalid"}, \
-  {"adjust-unroll", ADJUST_UNROLL_BIT, "Throttle unrolling to avoid thrashing target registers unless the unroll benefit outweighs this"}, \
-  {"no-adjust-unroll", -ADJUST_UNROLL_BIT, "Don't throttle unrolling"},
-#endif
-
-#define TARGET_SWITCHES \
-{ TARGET_SWITCH_SH1 \
-  TARGET_SWITCH_SH2 \
-  TARGET_SWITCH_SH2A_SINGLE_ONLY \
-  TARGET_SWITCH_SH2A_SINGLE \
-  TARGET_SWITCH_SH2A_NOFPU \
-  TARGET_SWITCH_SH2A \
-  TARGET_SWITCH_SH2E \
-  TARGET_SWITCH_SH3 \
-  TARGET_SWITCH_SH3E \
-  TARGET_SWITCH_SH4_SINGLE_ONLY \
-  TARGET_SWITCH_SH4_SINGLE \
-  TARGET_SWITCH_SH4_NOFPU \
-  TARGET_SWITCH_SH4 \
-  TARGET_SWITCH_SH4A_SINGLE_ONLY \
-  TARGET_SWITCH_SH4A_SINGLE \
-  TARGET_SWITCH_SH4A_NOFPU \
-  TARGET_SWITCH_SH4A \
-  TARGET_SWITCH_SH4AL \
-  TARGET_SWITCH_SH5_64MEDIA \
-  TARGET_SWITCH_SH5_64MEDIA_NOFPU \
-  TARGET_SWITCHES_SH5_32MEDIA \
-  TARGET_SWITCHES_SH5_32MEDIA_NOFPU \
-  {"b",		-LITTLE_ENDIAN_BIT, "Generate code in big endian mode" }, \
-  {"bigtable", 	BIGTABLE_BIT, "Generate 32-bit offsets in switch tables" }, \
-  {"dalign",  	DALIGN_BIT, "Aligns doubles at 64-bit boundaries" },	\
-  {"fmovd",  	FMOVD_BIT, "" },					\
-  {"hitachi",	HITACHI_BIT, "Follow Renesas (formerly Hitachi) / SuperH calling conventions" }, \
-  {"renesas",	HITACHI_BIT, "Follow Renesas (formerly Hitachi) / SuperH calling conventions" }, \
-  {"no-renesas",-HITACHI_BIT,"Follow the GCC calling conventions" },	\
-  {"nomacsave", NOMACSAVE_BIT, "Mark MAC register as call-clobbered" },	\
-  {"ieee",  	IEEE_BIT, "Increase the IEEE compliance for floating-point code" }, \
-  {"isize", 	ISIZE_BIT, "Annotate assembler instructions with estimated addresses" }, \
-  {"l",		LITTLE_ENDIAN_BIT, "Generate code in little endian mode" }, \
-  {"no-ieee",  	-IEEE_BIT, "Opposite of -mieee" },			\
-  {"padstruct", PADSTRUCT_BIT, "Make structs a multiple of 4 bytes (warning: ABI altered)" }, \
-  {"prefergot",	PREFERGOT_BIT, "Emit function-calls using global offset table when generating PIC" }, \
-  {"relax",	RELAX_BIT, "Shorten address references during linking" }, \
-  {"space", 	SPACE_BIT, "Deprecated. Use -Os instead" },		\
-  {"usermode",	USERMODE_BIT, "Generate library function call to invalidate instruction cache entries after fixing trampoline" }, \
-  TARGET_SWITCH_SH5_32_ANY_EXTRA \
-  TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA \
-  SUBTARGET_SWITCHES                            			\
-  {"",   	TARGET_DEFAULT, "" }					\
-}
-
-/* This are meant to be redefined in the host dependent files */
-#define SUBTARGET_SWITCHES
+#define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
+		   | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
+		   | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5)
 
 /* This defaults us to big-endian.  */
 #ifndef TARGET_ENDIAN_DEFAULT
@@ -647,7 +328,7 @@ extern int target_flags;
 #endif
 
 #ifndef TARGET_OPT_DEFAULT
-#define TARGET_OPT_DEFAULT  ADJUST_UNROLL_BIT
+#define TARGET_OPT_DEFAULT  MASK_ADJUST_UNROLL
 #endif
 
 #define TARGET_DEFAULT \
@@ -705,7 +386,7 @@ extern int target_flags;
   { "subtarget_asm_spec", SUBTARGET_ASM_SPEC },			\
   SUBTARGET_EXTRA_SPECS
 
-#if TARGET_CPU_DEFAULT & HARD_SH4_BIT
+#if TARGET_CPU_DEFAULT & MASK_HARD_SH4
 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4}}}}"
 #else
 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4}"
@@ -726,7 +407,7 @@ extern int target_flags;
 #define ASM_SPEC SH_ASM_SPEC
 
 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
-#if TARGET_ENDIAN_DEFAULT == LITTLE_ENDIAN_BIT
+#if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
 #else
 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
@@ -736,7 +417,7 @@ extern int target_flags;
 #if STRICT_NOFPU == 1
 /* Strict nofpu means that the compiler should tell the assembler
    to reject FPU instructions. E.g. from ASM inserts.  */
-#if TARGET_CPU_DEFAULT & HARD_SH4_BIT && !(TARGET_CPU_DEFAULT & SH_E_BIT)
+#if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
 #else
 /* If there were an -isa option for sh5-nofpu then it would also go here. */
@@ -751,30 +432,30 @@ extern int target_flags;
 #define SUBTARGET_ASM_SPEC ""
 #endif
 
-#if TARGET_ENDIAN_DEFAULT == LITTLE_ENDIAN_BIT
+#if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
 #define LINK_EMUL_PREFIX "sh%{!mb:l}"
 #else
 #define LINK_EMUL_PREFIX "sh%{ml:l}"
 #endif
 
-#if TARGET_CPU_DEFAULT & SH5_BIT
-#if TARGET_CPU_DEFAULT & SH_E_BIT
+#if TARGET_CPU_DEFAULT & MASK_SH5
+#if TARGET_CPU_DEFAULT & MASK_SH_E
 #define LINK_DEFAULT_CPU_EMUL "32"
-#if TARGET_CPU_DEFAULT & SH1_BIT
+#if TARGET_CPU_DEFAULT & MASK_SH1
 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
 #else
 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
-#endif /* SH1_BIT */
-#else /* !SH_E_BIT */
+#endif /* MASK_SH1 */
+#else /* !MASK_SH_E */
 #define LINK_DEFAULT_CPU_EMUL "64"
 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
-#endif /* SH_E_BIT */
+#endif /* MASK_SH_E */
 #define ASM_ISA_DEFAULT_SPEC \
 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
-#else /* !SH5_BIT */
+#else /* !MASK_SH5 */
 #define LINK_DEFAULT_CPU_EMUL ""
 #define ASM_ISA_DEFAULT_SPEC ""
-#endif /* SH5_BIT */
+#endif /* MASK_SH5 */
 
 #define SUBTARGET_LINK_EMUL_SUFFIX ""
 #define SUBTARGET_LINK_SPEC ""
@@ -806,7 +487,7 @@ do {									\
     }									\
   if (SIZE)								\
     {									\
-      target_flags |= SPACE_BIT;					\
+      target_flags |= MASK_SMALLCODE;					\
       sh_div_str = SH_DIV_STR_FOR_SIZE ;				\
     }									\
   /* We can't meaningfully test TARGET_SHMEDIA here, because -m options	\
@@ -817,7 +498,7 @@ do {									\
     {									\
       flag_branch_target_load_optimize = 1;				\
       if (! (SIZE))							\
-	target_flags |= SAVE_ALL_TR_BIT;				\
+	target_flags |= MASK_SAVE_ALL_TARGET_REGS;			\
     }									\
   /* Likewise, we can't meaningfully test TARGET_SH2E / TARGET_IEEE	\
      here, so leave it to OVERRIDE_OPTIONS to set			\
@@ -857,7 +538,7 @@ do {									\
     flag_finite_math_only						\
       = !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE;		\
   if (TARGET_SH2E && !flag_finite_math_only)				\
-    target_flags |= IEEE_BIT;						\
+    target_flags |= MASK_IEEE;						\
   sh_cpu = CPU_SH1;							\
   assembler_dialect = 0;						\
   if (TARGET_SH2)							\
@@ -868,7 +549,7 @@ do {									\
     {									\
       sh_cpu = CPU_SH2A;						\
       if (TARGET_SH2A_DOUBLE)						\
-        target_flags |= FMOVD_BIT;					\
+        target_flags |= MASK_FMOVD;					\
     }									\
   if (TARGET_SH3)							\
     sh_cpu = CPU_SH3;							\
@@ -887,15 +568,15 @@ do {									\
   if (TARGET_SH5)							\
     {									\
       sh_cpu = CPU_SH5;							\
-      target_flags |= DALIGN_BIT;					\
+      target_flags |= MASK_ALIGN_DOUBLE;				\
       if (TARGET_SHMEDIA_FPU)						\
-	target_flags |= FMOVD_BIT;					\
+	target_flags |= MASK_FMOVD;					\
       if (TARGET_SHMEDIA)						\
 	{								\
 	  /* There are no delay slots on SHmedia.  */			\
 	  flag_delayed_branch = 0;					\
 	  /* Relaxation isn't yet supported for SHmedia */		\
-	  target_flags &= ~RELAX_BIT;					\
+	  target_flags &= ~MASK_RELAX;					\
 	  /* After reload, if conversion does little good but can cause \
 	     ICEs:							\
 	     - find_if_block doesn't do anything for SH because we don't\
diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt
new file mode 100644
index 0000000..c3c659f
--- /dev/null
+++ b/gcc/config/sh/sh.opt
@@ -0,0 +1,214 @@
+; Options for the SH port of the compiler.
+
+; Copyright (C) 2005 Free Software Foundation, Inc.
+;
+; This file is part of GCC.
+;
+; GCC is free software; you can redistribute it and/or modify it under
+; the terms of the GNU General Public License as published by the Free
+; Software Foundation; either version 2, or (at your option) any later
+; version.
+;
+; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+; WARRANTY; without even the implied warranty of MERCHANTABILITY or
+; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+; for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with GCC; see the file COPYING.  If not, write to the Free
+; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+; 02111-1307, USA.
+
+;; Used for various architecture options.
+Mask(SH_E)
+
+;; Set if the default precision of th FPU is single.
+Mask(FPU_SINGLE)
+
+;; Set if we should generate code using type 2A insns.
+Mask(HARD_SH2A)
+
+;; Set if we should generate code using type 2A DF insns.
+Mask(HARD_SH2A_DOUBLE)
+
+;; Set if compiling for SH4 hardware (to be used for insn costs etc.)
+Mask(HARD_SH4)
+
+;; Set if we should generate code for a SH5 CPU (either ISA).
+Mask(SH5)
+
+;; Set if we should save all target registers.
+Mask(SAVE_ALL_TARGET_REGS)
+
+m1
+Target RejectNegative Mask(SH1) Condition(SUPPORT_SH1)
+Generate SH1 code
+
+m2
+Target RejectNegative Mask(SH2) Condition(SUPPORT_SH2)
+Generate SH2 code
+
+m2a
+Target RejectNegative Condition(SUPPORT_SH2A)
+Generate SH2a code
+
+m2a-nofpu
+Target RejectNegative Condition(SUPPORT_SH2A_NOFPU)
+Generate SH2a FPU-less code
+
+m2a-single
+Target RejectNegative Condition (SUPPORT_SH2A_SINGLE)
+Generate default single-precision SH2a code
+
+m2a-single-only
+Target RejectNegative Condition (SUPPORT_SH2A_SINGLE_ONLY)
+Generate only single-precision SH2a code
+
+m2e
+Target RejectNegative Condition(SUPPORT_SH2E)
+Generate SH2e code
+
+m3
+Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3)
+Generate SH3 code
+
+m3e
+Target RejectNegative Condition(SUPPORT_SH3E)
+Generate SH3e code
+
+m4
+Target RejectNegative Mask(SH4) Condition(SUPPORT_SH4)
+Generate SH4 code
+
+m4-nofpu
+Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
+Generate SH4 FPU-less code
+
+m4-single
+Target RejectNegative Condition(SUPPORT_SH4_SINGLE)
+Generate default single-precision SH4 code
+
+m4-single-only
+Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
+Generate only single-precision SH4 code
+
+m4a
+Target RejectNegative Mask(SH4A) Condition(SUPPORT_SH4A)
+Generate SH4a code
+
+m4a-nofpu
+Target RejectNegative Condition(SUPPORT_SH4A_NOFPU)
+Generate SH4a FPU-less code
+
+m4a-single
+Target RejectNegative Condition(SUPPORT_SH4A_SINGLE)
+Generate default single-precision SH4a code
+
+m4a-single-only
+Target RejectNegative Condition(SUPPORT_SH4A_SINGLE_ONLY)
+Generate only single-precision SH4a code
+
+m4al
+Target RejectNegative Condition(SUPPORT_SH4AL)
+Generate SH4al-dsp code
+
+m5-32media
+Target RejectNegative Condition(SUPPORT_SH5_32MEDIA)
+Generate 32-bit SHmedia code
+
+m5-32media-nofpu
+Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU)
+Generate 32-bit FPU-less SHmedia code
+
+m5-64media
+Target RejectNegative Condition(SUPPORT_SH5_64MEDIA)
+Generate 64-bit SHmedia code
+
+m5-64media-nofpu
+Target RejectNegative Condition(SUPPORT_SH5_64MEDIA_NOFPU)
+Generate 64-bit FPU-less SHmedia code
+
+m5-compact
+Target RejectNegative Condition(SUPPORT_SH5_32MEDIA)
+Generate SHcompact code
+
+m5-compact-nofpu
+Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU)
+Generate FPU-less SHcompact code
+
+madjust-unroll
+Target Report Mask(ADJUST_UNROLL) Condition(SUPPORT_ANY_SH5)
+Throttle unrolling to avoid thrashing target registers unless the unroll benefit outweighs this
+
+mb
+Target Report RejectNegative InverseMask(LITTLE_ENDIAN)
+Generate code in big endian mode
+
+mbigtable
+Target Report RejectNegative Mask(BIGTABLE)
+Generate 32-bit offsets in switch tables
+
+mdalign
+Target Report RejectNegative Mask(ALIGN_DOUBLE)
+Align doubles at 64-bit boundaries
+
+mfmovd
+Target RejectNegative Mask(FMOVD) Undocumented
+
+mhitachi
+Target Report RejectNegative Mask(HITACHI)
+Follow Renesas (formerly Hitachi) / SuperH calling conventions
+
+mieee
+Target Report Mask(IEEE)
+Increase the IEEE compliance for floating-point code
+
+mindexed-addressing
+Target Report Mask(ALLOW_INDEXED_ADDRESS) Condition(SUPPORT_ANY_SH5_32MEDIA)
+Enable the use of the indexed addressing mode for SHmedia32/SHcompact
+
+minvalid-symbols
+Target Report Mask(INVALID_SYMBOLS) Condition(SUPPORT_ANY_SH5)
+Assume symbols might be invalid
+
+misize
+Target Report RejectNegative Mask(DUMPISIZE)
+Annotate assembler instructions with estimated addresses
+
+ml
+Target Report RejectNegative Mask(LITTLE_ENDIAN)
+Generate code in little endian mode
+
+mnomacsave
+Target Report RejectNegative Mask(NOMACSAVE)
+Mark MAC register as call-clobbered
+
+;; ??? This option is not useful, but is retained in case there are people
+;; who are still relying on it.  It may be deleted in the future.
+mpadstruct
+Target Report RejectNegative Mask(PADSTRUCT)
+Make structs a multiple of 4 bytes (warning: ABI altered)
+
+mprefergot
+Target Report RejectNegative Mask(PREFERGOT)
+Emit function-calls using global offset table when generating PIC
+
+mpt-fixed
+Target Report Mask(PT_FIXED) Condition(SUPPORT_ANY_SH5)
+Assume pt* instructions won't trap
+
+mrelax
+Target Report RejectNegative Mask(RELAX)
+Shorten address references during linking
+
+mrenesas
+Target Mask(HITACHI) MaskExists
+Follow Renesas (formerly Hitachi) / SuperH calling conventions
+
+mspace
+Target Report RejectNegative Mask(SMALLCODE)
+Deprecated. Use -Os instead
+
+musermode
+Target Report RejectNegative Mask(USERMODE)
+Generate library function call to invalidate instruction cache entries after fixing trampoline
diff --git a/gcc/config/sh/symbian-pre.h b/gcc/config/sh/symbian-pre.h
index 53e2d92..1d882be 100644
--- a/gcc/config/sh/symbian-pre.h
+++ b/gcc/config/sh/symbian-pre.h
@@ -25,7 +25,7 @@
 #define SYMBIAN		1
 
 /* Default to using the Renesas ABI.  */
-#define TARGET_ABI_DEFAULT	RENESAS_BIT
+#define TARGET_ABI_DEFAULT	MASK_HITACHI
 
 #define SUBTARGET_CPP_SPEC ""