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| author | Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org> | 2025-01-20 10:01:09 +0100 |
|---|---|---|
| committer | Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org> | 2025-01-20 10:01:09 +0100 |
| commit | f31ddaaaa2d9e683ddd8534663af092984ddb911 (patch) | |
| tree | f59a963a5b79af4ddb53321666293a833f361023 /gcc/config/s390 | |
| parent | 0f0b91ef70218e2cb4ab795ef04725a68ea04b15 (diff) | |
| download | gcc-f31ddaaaa2d9e683ddd8534663af092984ddb911.zip gcc-f31ddaaaa2d9e683ddd8534663af092984ddb911.tar.gz gcc-f31ddaaaa2d9e683ddd8534663af092984ddb911.tar.bz2 | |
s390: arch15: Vector devide/remainder
gcc/ChangeLog:
* config/s390/vector.md (div<mode>3): Add.
(udiv<mode>3): Add.
(mod<mode>3): Add.
(umod<mode>3): Add.
gcc/testsuite/ChangeLog:
* gcc.target/s390/vxe3/vd-1.c: New test.
* gcc.target/s390/vxe3/vd-2.c: New test.
* gcc.target/s390/vxe3/vdl-1.c: New test.
* gcc.target/s390/vxe3/vdl-2.c: New test.
* gcc.target/s390/vxe3/vr-1.c: New test.
* gcc.target/s390/vxe3/vr-2.c: New test.
* gcc.target/s390/vxe3/vrl-1.c: New test.
* gcc.target/s390/vxe3/vrl-2.c: New test.
Diffstat (limited to 'gcc/config/s390')
| -rw-r--r-- | gcc/config/s390/vector.md | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index 2e7419c4..606c682 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -1145,6 +1145,42 @@ "vml<bhfgq><w>\t%v0,%v1,%v2" [(set_attr "op_type" "VRR")]) +; vdf, vdg, vdq +(define_insn "div<mode>3" + [(set (match_operand:VI_HW_SDT 0 "register_operand" "=v") + (div:VI_HW_SDT (match_operand:VI_HW_SDT 1 "register_operand" "v") + (match_operand:VI_HW_SDT 2 "register_operand" "v")))] + "TARGET_VXE3" + "vd<bhfgq>\t%v0,%v1,%v2,0" + [(set_attr "op_type" "VRR")]) + +; vdlf, vdlg, vdlq +(define_insn "udiv<mode>3" + [(set (match_operand:VI_HW_SDT 0 "register_operand" "=v") + (udiv:VI_HW_SDT (match_operand:VI_HW_SDT 1 "register_operand" "v") + (match_operand:VI_HW_SDT 2 "register_operand" "v")))] + "TARGET_VXE3" + "vdl<bhfgq>\t%v0,%v1,%v2,0" + [(set_attr "op_type" "VRR")]) + +; vrf, vrg, vrq +(define_insn "mod<mode>3" + [(set (match_operand:VI_HW_SDT 0 "register_operand" "=v") + (mod:VI_HW_SDT (match_operand:VI_HW_SDT 1 "register_operand" "v") + (match_operand:VI_HW_SDT 2 "register_operand" "v")))] + "TARGET_VXE3" + "vr<bhfgq>\t%v0,%v1,%v2,0" + [(set_attr "op_type" "VRR")]) + +; vrlf, vrlg, vrlq +(define_insn "umod<mode>3" + [(set (match_operand:VI_HW_SDT 0 "register_operand" "=v") + (umod:VI_HW_SDT (match_operand:VI_HW_SDT 1 "register_operand" "v") + (match_operand:VI_HW_SDT 2 "register_operand" "v")))] + "TARGET_VXE3" + "vrl<bhfgq>\t%v0,%v1,%v2,0" + [(set_attr "op_type" "VRR")]) + ; vlcb, vlch, vlcf, vlcg (define_insn "neg<mode>2" [(set (match_operand:VI 0 "register_operand" "=v") |