s390: Extend two/four element integer vectors

For the moment I deliberately left out one-element QHS vectors since it
is unclear whether these are pathological cases or whether they are
really used.  If we ever get an extend for V1DI -> V1TI we should
reconsider this.

As a side-effect this fixes PR115261.

gcc/ChangeLog:

	PR target/115261
	* config/s390/s390.md (any_extend,extend_insn,zero_extend):
	New code attributes and code iterator.
	* config/s390/vector.md (V_EXTEND): New mode iterator.
	(<extend_insn><V_EXTEND:mode><vec_2x_wide>2): New insn.

gcc/testsuite/ChangeLog:

	* gcc.target/s390/vector/vec-extend-1.c: New test.
	* gcc.target/s390/vector/vec-extend-2.c: New test.

2 files changed, 28 insertions, 5 deletions

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index c607dce..1311a5f 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -602,6 +602,10 @@
 
 (define_attr "relative_long" "no,yes" (const_string "no"))
 
+(define_code_attr extend_insn [(sign_extend "extend") (zero_extend "zero_extend")])
+(define_code_attr zero_extend [(sign_extend "") (zero_extend "l")])
+(define_code_iterator any_extend [sign_extend zero_extend])
+
 ;; Pipeline description for z900.
 (include "2064.md")
 
diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index ed4742d..a931a4b 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -87,6 +87,8 @@
 ; 32 bit int<->fp vector conversion instructions are available since VXE2 (z15).
 (define_mode_iterator VX_VEC_CONV_BFP [V2DF (V4SF "TARGET_VXE2")])
 
+(define_mode_iterator VI_EXTEND [V2QI V2HI V2SI V4QI V4HI])
+
 ; Empty string for all but TImode.  This is used to hide the TImode
 ; expander name in case it is defined already.  See addti3 for an
 ; example.
@@ -195,13 +197,20 @@
 				(V1DF "V2DF") (V2DF "V4DF")])
 
 ; Vector with widened element size and the same number of elements.
-(define_mode_attr vec_2x_wide [(V1QI "V1HI") (V2QI "V2HI") (V4QI "V4HI") (V8QI "V8HI") (V16QI "V16HI")
+(define_mode_attr VEC_2X_WIDE [(V1QI "V1HI") (V2QI "V2HI") (V4QI "V4HI") (V8QI "V8HI") (V16QI "V16HI")
 			       (V1HI "V1SI") (V2HI "V2SI") (V4HI "V4SI") (V8HI "V8SI")
 			       (V1SI "V1DI") (V2SI "V2DI") (V4SI "V4DI")
 			       (V1DI "V1TI") (V2DI "V2TI")
 			       (V1SF "V1DF") (V2SF "V2DF") (V4SF "V4DF")
 			       (V1DF "V1TF") (V2DF "V2TF")])
 
+(define_mode_attr vec_2x_wide [(V1QI "v1hi") (V2QI "v2hi") (V4QI "v4hi") (V8QI "v8hi") (V16QI "v16hi")
+			       (V1HI "v1si") (V2HI "v2si") (V4HI "v4si") (V8HI "v8si")
+			       (V1SI "v1di") (V2SI "v2di") (V4SI "v4di")
+			       (V1DI "v1ti") (V2DI "v2ti")
+			       (V1SF "v1df") (V2SF "v2df") (V4SF "v4df")
+			       (V1DF "v1tf") (V2DF "v2tf")])
+
 ; Vector with half the element size AND half the number of elements.
 (define_mode_attr vec_halfhalf
   [(V2HI "V2QI") (V4HI "V4QI") (V8HI "V8QI")
@@ -1604,7 +1613,7 @@
 			     UNSPEC_VEC_UMULT_ODD))
    (set (match_operand:<vec_double>                 0 "register_operand" "")
         (vec_select:<vec_double>
-	 (vec_concat:<vec_2x_wide> (match_dup 3) (match_dup 4))
+	 (vec_concat:<VEC_2X_WIDE> (match_dup 3) (match_dup 4))
 	 (match_dup 5)))]
   "TARGET_VX"
  {
@@ -1623,7 +1632,7 @@
 			     UNSPEC_VEC_UMULT_ODD))
    (set (match_operand:<vec_double>                 0 "register_operand" "")
         (vec_select:<vec_double>
-	 (vec_concat:<vec_2x_wide> (match_dup 3) (match_dup 4))
+	 (vec_concat:<VEC_2X_WIDE> (match_dup 3) (match_dup 4))
 	 (match_dup 5)))]
   "TARGET_VX"
  {
@@ -1642,7 +1651,7 @@
 			     UNSPEC_VEC_SMULT_ODD))
    (set (match_operand:<vec_double>                 0 "register_operand" "")
         (vec_select:<vec_double>
-	 (vec_concat:<vec_2x_wide> (match_dup 3) (match_dup 4))
+	 (vec_concat:<VEC_2X_WIDE> (match_dup 3) (match_dup 4))
 	 (match_dup 5)))]
   "TARGET_VX"
  {
@@ -1661,7 +1670,7 @@
 			     UNSPEC_VEC_SMULT_ODD))
    (set (match_operand:<vec_double>                 0 "register_operand" "")
         (vec_select:<vec_double>
-	 (vec_concat:<vec_2x_wide> (match_dup 3) (match_dup 4))
+	 (vec_concat:<VEC_2X_WIDE> (match_dup 3) (match_dup 4))
 	 (match_dup 5)))]
   "TARGET_VX"
  {
@@ -2375,6 +2384,16 @@
   "vpkls<bhfgq>\t%0,%1,%2"
   [(set_attr "op_type" "VRR")])
 
+;; vector unpack / extend
+
+(define_insn "<extend_insn><VI_EXTEND:mode><vec_2x_wide>2"
+  [(set (match_operand:<VEC_2X_WIDE> 0 "register_operand" "=v")
+	(any_extend:<VEC_2X_WIDE>
+	 (match_operand:VI_EXTEND 1 "register_operand" "v")))]
+  "TARGET_VX"
+  "vup<zero_extend>h<bhfgq>\t%0,%1"
+  [(set_attr "op_type" "VRR")])
+
 ;; vector unpack v16qi
 
 ; signed