diff options
author | Andreas Krebbel <krebbel@linux.ibm.com> | 2021-08-04 18:40:09 +0200 |
---|---|---|
committer | Andreas Krebbel <krebbel@linux.ibm.com> | 2021-08-04 18:40:09 +0200 |
commit | 0aa7091befa9fdb67f7013dbd454d336a31ef71d (patch) | |
tree | 8f556be8265a6a1aac5c8d6853e82ce9d7676269 /gcc/config/s390 | |
parent | 5391688acc997e26375e42340cea885fa6ad0d7d (diff) | |
download | gcc-0aa7091befa9fdb67f7013dbd454d336a31ef71d.zip gcc-0aa7091befa9fdb67f7013dbd454d336a31ef71d.tar.gz gcc-0aa7091befa9fdb67f7013dbd454d336a31ef71d.tar.bz2 |
IBM Z: Get rid of vpdi unspec
The patch gets rid of the unspec used for the vector permute double
immediate instruction and replaces it with generic rtx.
gcc/ChangeLog:
* config/s390/s390.md (UNSPEC_VEC_PERMI): Remove constant
definition.
* config/s390/vector.md (*vpdi1<mode>, *vpdi4<mode>): New pattern
definitions.
* config/s390/vx-builtins.md (*vec_permi<mode>): Emit generic rtx
instead of an unspec.
gcc/testsuite/ChangeLog:
* gcc.target/s390/zvector/vec-permi.c: Removed.
* gcc.target/s390/zvector/vec_permi.c: New test.
Diffstat (limited to 'gcc/config/s390')
-rw-r--r-- | gcc/config/s390/s390.md | 1 | ||||
-rw-r--r-- | gcc/config/s390/vector.md | 26 | ||||
-rw-r--r-- | gcc/config/s390/vx-builtins.md | 26 |
3 files changed, 36 insertions, 17 deletions
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index d896fae..1b894a9 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -166,7 +166,6 @@ UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC UNSPEC_VEC_PERM - UNSPEC_VEC_PERMI UNSPEC_VEC_EXTEND UNSPEC_VEC_STORE_LEN UNSPEC_VEC_STORE_LEN_R diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index 51c6332..48dc564 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -767,6 +767,32 @@ "vperm\t%v0,%v1,%v2,%v3" [(set_attr "op_type" "VRR")]) + +; First DW of op1 and second DW of op2 +(define_insn "*vpdi1<mode>" + [(set (match_operand:V_HW_2 0 "register_operand" "=v") + (vec_select:V_HW_2 + (vec_concat:<vec_2x_nelts> + (match_operand:V_HW_2 1 "register_operand" "v") + (match_operand:V_HW_2 2 "register_operand" "v")) + (parallel [(const_int 0) (const_int 3)])))] + "TARGET_VX" + "vpdi\t%v0,%v1,%v2,1" + [(set_attr "op_type" "VRR")]) + +; Second DW of op1 and first of op2 +(define_insn "*vpdi4<mode>" + [(set (match_operand:V_HW_2 0 "register_operand" "=v") + (vec_select:V_HW_2 + (vec_concat:<vec_2x_nelts> + (match_operand:V_HW_2 1 "register_operand" "v") + (match_operand:V_HW_2 2 "register_operand" "v")) + (parallel [(const_int 1) (const_int 2)])))] + "TARGET_VX" + "vpdi\t%v0,%v1,%v2,4" + [(set_attr "op_type" "VRR")]) + + (define_insn "*vmrhb" [(set (match_operand:V16QI 0 "register_operand" "=v") (vec_select:V16QI diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md index 5abe43b..3799e83 100644 --- a/gcc/config/s390/vx-builtins.md +++ b/gcc/config/s390/vx-builtins.md @@ -403,28 +403,22 @@ "vperm\t%v0,%v1,%v2,%v3" [(set_attr "op_type" "VRR")]) +; Incoming op3 is in vec_permi format and will we turned into a +; permute vector consisting of op3 and op4. (define_expand "vec_permi<mode>" - [(set (match_operand:V_HW_64 0 "register_operand" "") - (unspec:V_HW_64 [(match_operand:V_HW_64 1 "register_operand" "") - (match_operand:V_HW_64 2 "register_operand" "") - (match_operand:QI 3 "const_mask_operand" "")] - UNSPEC_VEC_PERMI))] + [(set (match_operand:V_HW_2 0 "register_operand" "") + (vec_select:V_HW_2 + (vec_concat:<vec_2x_nelts> + (match_operand:V_HW_2 1 "register_operand" "") + (match_operand:V_HW_2 2 "register_operand" "")) + (parallel [(match_operand:QI 3 "const_mask_operand" "") (match_dup 4)])))] "TARGET_VX" { HOST_WIDE_INT val = INTVAL (operands[3]); - operands[3] = GEN_INT ((val & 1) | (val & 2) << 1); + operands[3] = GEN_INT ((val & 2) >> 1); + operands[4] = GEN_INT ((val & 1) + 2); }) -(define_insn "*vec_permi<mode>" - [(set (match_operand:V_HW_64 0 "register_operand" "=v") - (unspec:V_HW_64 [(match_operand:V_HW_64 1 "register_operand" "v") - (match_operand:V_HW_64 2 "register_operand" "v") - (match_operand:QI 3 "const_mask_operand" "C")] - UNSPEC_VEC_PERMI))] - "TARGET_VX && (UINTVAL (operands[3]) & 10) == 0" - "vpdi\t%v0,%v1,%v2,%b3" - [(set_attr "op_type" "VRR")]) - ; Vector replicate |