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| author | Devang Patel <dpatel@apple.com> | 2005-04-05 09:33:29 -0700 |
|---|---|---|
| committer | Devang Patel <dpatel@gcc.gnu.org> | 2005-04-05 09:33:29 -0700 |
| commit | 3e0de9d1880ccba36323b5d6c81bc2a0bae912f8 (patch) | |
| tree | 14d011f90dd136d023b5c2f138e870718fc7a295 /gcc/config/rs6000 | |
| parent | e72f3fa192d67670fe3cbdb34b3b590054b684d5 (diff) | |
| download | gcc-3e0de9d1880ccba36323b5d6c81bc2a0bae912f8.zip gcc-3e0de9d1880ccba36323b5d6c81bc2a0bae912f8.tar.gz gcc-3e0de9d1880ccba36323b5d6c81bc2a0bae912f8.tar.bz2 | |
altivec.md (altivec_vsr<VI_char>): Rename to ..
* config/rs600/altivec.md (altivec_vsr<VI_char>): Rename to ..
(lhsr<mode>3): ... new name.
(altivec_vsra<VI_char>): Rename to ..
(ashr<mode>3): ... new name.
* config/rs6000/rs6000.c (builtin_description): Rename shift
operations.
testsuite:
* lib/target-supports.exp (check_effective_target_vect_shif): New.
* gcc.dg/vect/vect-shift-1.c: New test.
From-SVN: r97636
Diffstat (limited to 'gcc/config/rs6000')
| -rw-r--r-- | gcc/config/rs6000/altivec.md | 12 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 12 |
2 files changed, 12 insertions, 12 deletions
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 9e98ffe..d455dda 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -968,18 +968,18 @@ "vslo %0,%1,%2" [(set_attr "type" "vecperm")]) -(define_insn "altivec_vsr<VI_char>" +(define_insn "lshr<mode>3" [(set (match_operand:VI 0 "register_operand" "=v") - (unspec:VI [(match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v")] 112))] + (lshiftrt:VI (match_operand:VI 1 "register_operand" "v") + (match_operand:VI 2 "register_operand" "v") ))] "TARGET_ALTIVEC" "vsr<VI_char> %0,%1,%2" [(set_attr "type" "vecsimple")]) -(define_insn "altivec_vsra<VI_char>" +(define_insn "ashr<mode>3" [(set (match_operand:VI 0 "register_operand" "=v") - (unspec:VI [(match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v")] 115))] + (ashiftrt:VI (match_operand:VI 1 "register_operand" "v") + (match_operand:VI 2 "register_operand" "v") ))] "TARGET_ALTIVEC" "vsra<VI_char> %0,%1,%2" [(set_attr "type" "vecsimple")]) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index d732843..8ca07a2 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -5590,12 +5590,12 @@ static struct builtin_description bdesc_2arg[] = { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB }, { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH }, { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW }, - { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB }, - { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH }, - { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW }, - { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB }, - { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH }, - { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW }, + { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB }, + { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH }, + { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW }, + { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB }, + { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH }, + { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW }, { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR }, { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO }, { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM }, |