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| author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2017-07-24 20:02:33 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2017-07-24 20:02:33 +0000 |
| commit | 1993098939aa6033abb75961127c25e316864501 (patch) | |
| tree | db97d4a0d558a0da8a87271348dde0a32414be59 /gcc/config/rs6000/rs6000.opt | |
| parent | 0281547a1d9637f60f93b361bce0b548df120962 (diff) | |
| download | gcc-1993098939aa6033abb75961127c25e316864501.zip gcc-1993098939aa6033abb75961127c25e316864501.tar.gz gcc-1993098939aa6033abb75961127c25e316864501.tar.bz2 | |
rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Delete upper-regs options.
[gcc]
2017-07-24 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Delete
upper-regs options.
(ISA_2_7_MASKS_SERVER): Likewise.
(ISA_3_0_MASKS_IEEE): Likewise.
(OTHER_P8_VECTOR_MASKS): Likewise.
(OTHER_VSX_VECTOR_MASKS): Likewise.
(POWERPC_MASKS): Likewise.
(power7 cpu): Use ISA_2_6_MASKS_SERVER instead of using a
duplicate list of options.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Remove
explicit -mupper-regs options.
* config/rs6000/rs6000.opt (-mvsx-scalar-memory): Delete
-mupper-regs* options. Delete -mvsx-scalar-memory, which was an
alias for -mupper-regs-df.
* config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Likewise.
(rs6000_init_hard_regno_mode_ok): Likewise.
(rs6000_option_override_internal): Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.h (TARGET_UPPER_REGS_DF): Define upper regs
options in terms of whether -mvsx or -mpower8-vector was used.
(TARGET_UPPER_REGS_DI): Likewise.
(TARGET_UPPER_REGS_SF): Likewise.
* doc/invoke.texi (RS/6000 and PowerPC Options): Delete the
-mupper-regs-* options.
[gcc/testsuite]
2017-07-24 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/pr65849-1.c: Delete, test no longer valid
since the upper-regs options have been deleted.
* gcc.target/powerpc/pr65849-2.c: Likewise.
* gcc.target/powerpc/pr80099-1.c: Likewise.
* gcc.target/powerpc/pr80099-2.c: Likewise.
* gcc.target/powerpc/pr80099-3.c: Likewise.
* gcc.target/powerpc/pr80099-4.c: Likewise.
* gcc.target/powerpc/pr80099-5.c: Likewise.
* gcc.target/powerpc/builtins-2-p9-runnable.c: Update test to
support removal of the upper-regs options.
* gcc.target/powerpc/p8vector-fp.c: Likewise.
* gcc.target/powerpc/p8vector-ldst.c: Likewise.
* gcc.target/powerpc/p9-dimode1.c: Likewise.
* gcc.target/powerpc/p9-dimode2.c: Likewise.
* gcc.target/powerpc/ppc-fpconv-1.c: Likewise.
* gcc.target/powerpc/ppc-fpconv-10.c: Likewise.
* gcc.target/powerpc/ppc-fpconv-5.c: Likewise.
* gcc.target/powerpc/ppc-fpconv-9.c: Likewise.
* gcc.target/powerpc/ppc-round.c: Likewise.
* gcc.target/powerpc/pr71720.c: Likewise.
* gcc.target/powerpc/pr72853.c: Likewise.
* gcc.target/powerpc/pr79907.c: Likewise.
* gcc.target/powerpc/pr78953.c: Likewise.
* gcc.target/powerpc/upper-regs-df.c: Likewise.
* gcc.target/powerpc/upper-regs-sf.c: Likewise.
* gcc.target/powerpc/vec-extract-1.c: Likewise.
* gcc.target/powerpc/vec-init-3.c: Likewise.
* gcc.target/powerpc/vec-init-6.c: Likewise.
* gcc.target/powerpc/vec-init-7.c: Likewise.
* gcc.target/powerpc/vec-set-char.c: Likewise.
* gcc.target/powerpc/vec-set-int.c: Likewise.
* gcc.target/powerpc/vec-set-short.c: Likewise.
From-SVN: r250482
Diffstat (limited to 'gcc/config/rs6000/rs6000.opt')
| -rw-r--r-- | gcc/config/rs6000/rs6000.opt | 19 |
1 files changed, 0 insertions, 19 deletions
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 28d8993..9a36844 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -200,9 +200,6 @@ mvsx-scalar-double Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(1) ; If -mvsx, use VSX arithmetic instructions for DFmode (on by default) -mvsx-scalar-memory -Target Undocumented Report Alias(mupper-regs-df) - mvsx-align-128 Target Undocumented Report Var(TARGET_VSX_ALIGN_128) Save ; If -mvsx, set alignment to 128 bits instead of 32/64 @@ -549,22 +546,6 @@ mcompat-align-parm Target Report Var(rs6000_compat_align_parm) Init(0) Save Generate aggregate parameter passing code with at most 64-bit alignment. -mupper-regs-df -Target Report Mask(UPPER_REGS_DF) Var(rs6000_isa_flags) -Allow double variables in upper registers with -mcpu=power7 or -mvsx. - -mupper-regs-sf -Target Report Mask(UPPER_REGS_SF) Var(rs6000_isa_flags) -Allow float variables in upper registers with -mcpu=power8 or -mpower8-vector. - -mupper-regs -Target Report Var(TARGET_UPPER_REGS) Init(-1) Save -Allow float/double variables in upper registers if cpu allows it. - -mupper-regs-di -Target Report Mask(UPPER_REGS_DI) Var(rs6000_isa_flags) -Allow 64-bit integer variables in upper registers with -mcpu=power7 or -mvsx. - moptimize-swaps Target Undocumented Var(rs6000_optimize_swaps) Init(1) Save Analyze and remove doubleword swaps from VSX computations. |