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| author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2016-06-29 23:54:12 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2016-06-29 23:54:12 +0000 |
| commit | c5e74d9d4ebeb29fab731464c206296ec651e9a6 (patch) | |
| tree | c8f3aa2d947baf993d1bf23e77219924e9a4c969 /gcc/config/rs6000/rs6000.md | |
| parent | e44ecbfd9fde1d4d715c30f584f7cc8e535c749f (diff) | |
| download | gcc-c5e74d9d4ebeb29fab731464c206296ec651e9a6.zip gcc-c5e74d9d4ebeb29fab731464c206296ec651e9a6.tar.gz gcc-c5e74d9d4ebeb29fab731464c206296ec651e9a6.tar.bz2 | |
predicates.md (const_0_to_7_operand): New predicate, recognize 0..7.
[gcc]
2016-06-29 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/predicates.md (const_0_to_7_operand): New
predicate, recognize 0..7.
* config/rs6000/rs6000.c (rs6000_expand_vector_extract): Add
support for doing extracts from V16QImode, V8HImode, V4SImode
under ISA 3.0.
* config/rs6000/vsx.md (VSX_EXTRACT_I): Mode iterator for ISA 3.0
vector extract support.
(VSX_EXTRACT_PREDICATE): Mode attribute to validate element number
for ISA 3.0 vector extract.
(VSX_EX): Constraints to use for ISA 3.0 vector extract.
(vsx_extract_<mode>, VSX_EXTRACT_I): Add support for doing
extracts of a constant element number from small integer vectors
on 64-bit ISA 3.0 systems.
(vsx_extract_<mode>_di): Likewise.
* config/rs6000/rs6000.h (TARGET_VEXTRACTUB): New target macro to
say when we can do ISA 3.0 vector extracts.
* config/rs6000/rs6000.md (stfiwx): Allow DImode in Altivec
registers, using the stxsiwx instruction.
[gcc/testsuite]
2016-06-29 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/p9-extract-1.c: New file to test ISA 3.0
vector extract instructions.
* gcc.target/powerpc/p9-extract-2.c: Likewise.
From-SVN: r237864
Diffstat (limited to 'gcc/config/rs6000/rs6000.md')
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 12f5d6f..81d189b 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -5696,11 +5696,13 @@ ; An UNSPEC is used so we don't have to support SImode in FP registers. (define_insn "stfiwx" - [(set (match_operand:SI 0 "memory_operand" "=Z") - (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")] + [(set (match_operand:SI 0 "memory_operand" "=Z,Z") + (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d,wv")] UNSPEC_STFIWX))] "TARGET_PPC_GFXOPT" - "stfiwx %1,%y0" + "@ + stfiwx %1,%y0 + stxsiwx %x1,%y0" [(set_attr "type" "fpstore")]) ;; If we don't have a direct conversion to single precision, don't enable this |