diff options
| author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2009-09-14 16:59:12 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2009-09-14 16:59:12 +0000 |
| commit | 5910fb59b9df9dbdde8a70a71609c4bc1467a29b (patch) | |
| tree | ad3c1fb09c7be8aee817570885e9f6f2a67e66cf /gcc/config/rs6000/rs6000.md | |
| parent | 6c1c1dfa24f6239c3d70c901693de65b3390da65 (diff) | |
| download | gcc-5910fb59b9df9dbdde8a70a71609c4bc1467a29b.zip gcc-5910fb59b9df9dbdde8a70a71609c4bc1467a29b.tar.gz gcc-5910fb59b9df9dbdde8a70a71609c4bc1467a29b.tar.bz2 | |
Fix PR 41210 & 41331 on powerpc
From-SVN: r151691
Diffstat (limited to 'gcc/config/rs6000/rs6000.md')
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 30 |
1 files changed, 16 insertions, 14 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index d7f30f8..8ea90d8 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -2392,9 +2392,11 @@ if (!REG_P (operands[0]) && !REG_P (operands[1])) operands[1] = force_reg (DImode, operands[1]); - if (TARGET_32BIT) + if (!TARGET_POWERPC64) { - /* 32-bit needs fewer scratch registers. */ + /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode + that uses 64-bit registers needs the same scratch registers as 64-bit + mode. */ emit_insn (gen_bswapdi2_32bit (operands[0], operands[1])); DONE; } @@ -2453,13 +2455,13 @@ addr1 = XEXP (src, 0); if (GET_CODE (addr1) == PLUS) { - emit_insn (gen_adddi3 (op2, XEXP (addr1, 0), GEN_INT (4))); - addr2 = gen_rtx_PLUS (DImode, op2, XEXP (addr1, 1)); + emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4))); + addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1)); } else { emit_move_insn (op2, GEN_INT (4)); - addr2 = gen_rtx_PLUS (DImode, op2, addr1); + addr2 = gen_rtx_PLUS (Pmode, op2, addr1); } if (BYTES_BIG_ENDIAN) @@ -2503,13 +2505,13 @@ addr1 = XEXP (dest, 0); if (GET_CODE (addr1) == PLUS) { - emit_insn (gen_adddi3 (op2, XEXP (addr1, 0), GEN_INT (4))); - addr2 = gen_rtx_PLUS (DImode, op2, XEXP (addr1, 1)); + emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4))); + addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1)); } else { emit_move_insn (op2, GEN_INT (4)); - addr2 = gen_rtx_PLUS (DImode, op2, addr1); + addr2 = gen_rtx_PLUS (Pmode, op2, addr1); } emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32))); @@ -2559,7 +2561,7 @@ [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r") (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r"))) (clobber (match_scratch:SI 2 "=&b,&b,X"))] - "TARGET_32BIT && (REG_P (operands[0]) || REG_P (operands[1]))" + "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))" "#" [(set_attr "length" "16,12,36")]) @@ -2567,7 +2569,7 @@ [(set (match_operand:DI 0 "gpc_reg_operand" "") (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" ""))) (clobber (match_operand:SI 2 "gpc_reg_operand" ""))] - "TARGET_32BIT && reload_completed" + "!TARGET_POWERPC64 && reload_completed" [(const_int 0)] " { @@ -2584,7 +2586,7 @@ addr1 = XEXP (src, 0); if (GET_CODE (addr1) == PLUS) { - emit_insn (gen_addsi3 (op2, XEXP (addr1, 0), GEN_INT (4))); + emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4))); addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1)); } else @@ -2612,7 +2614,7 @@ [(set (match_operand:DI 0 "indexed_or_indirect_operand" "") (bswap:DI (match_operand:DI 1 "gpc_reg_operand" ""))) (clobber (match_operand:SI 2 "gpc_reg_operand" ""))] - "TARGET_32BIT && reload_completed" + "!TARGET_POWERPC64 && reload_completed" [(const_int 0)] " { @@ -2629,7 +2631,7 @@ addr1 = XEXP (dest, 0); if (GET_CODE (addr1) == PLUS) { - emit_insn (gen_addsi3 (op2, XEXP (addr1, 0), GEN_INT (4))); + emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4))); addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1)); } else @@ -2657,7 +2659,7 @@ [(set (match_operand:DI 0 "gpc_reg_operand" "") (bswap:DI (match_operand:DI 1 "gpc_reg_operand" ""))) (clobber (match_operand:SI 2 "" ""))] - "TARGET_32BIT && reload_completed" + "!TARGET_POWERPC64 && reload_completed" [(const_int 0)] " { |