rs6000: correct vector sign extend builtins on Big Endian

gcc/
	PR target/108812
	* config/rs6000/vsx.md (vsx_sign_extend_qi_<mode>): Rename to...
	(vsx_sign_extend_v16qi_<mode>): ... this.
	(vsx_sign_extend_hi_<mode>): Rename to...
	(vsx_sign_extend_v8hi_<mode>): ... this.
	(vsx_sign_extend_si_v2di): Rename to...
	(vsx_sign_extend_v4si_v2di): ... this.
	(vsignextend_qi_<mode>): Remove.
	(vsignextend_hi_<mode>): Remove.
	(vsignextend_si_v2di): Remove.
	(vsignextend_v2di_v1ti): Remove.
	(*xxspltib_<mode>_split): Replace gen_vsx_sign_extend_qi_v2di with
	gen_vsx_sign_extend_v16qi_v2di and gen_vsx_sign_extend_qi_v4si
	with gen_vsx_sign_extend_v16qi_v4si.
	* config/rs6000/rs6000.md (split for DI constant generation):
	Replace gen_vsx_sign_extend_qi_si with gen_vsx_sign_extend_v16qi_si.
	(split for HSDI constant generation): Replace gen_vsx_sign_extend_qi_di
	with gen_vsx_sign_extend_v16qi_di and gen_vsx_sign_extend_qi_si
	with gen_vsx_sign_extend_v16qi_si.
	* config/rs6000/rs6000-builtins.def (__builtin_altivec_vsignextsb2d):
	Set bif-pattern to vsx_sign_extend_v16qi_v2di.
	(__builtin_altivec_vsignextsb2w): Set bif-pattern to
	vsx_sign_extend_v16qi_v4si.
	(__builtin_altivec_visgnextsh2d): Set bif-pattern to
	vsx_sign_extend_v8hi_v2di.
	(__builtin_altivec_vsignextsh2w): Set bif-pattern to
	vsx_sign_extend_v8hi_v4si.
	(__builtin_altivec_vsignextsw2d): Set bif-pattern to
	vsx_sign_extend_si_v2di.
	(__builtin_altivec_vsignext): Set bif-pattern to
	vsx_sign_extend_v2di_v1ti.
	* config/rs6000/rs6000-builtin.cc (lxvrse_expand_builtin): Replace
	gen_vsx_sign_extend_qi_v2di with gen_vsx_sign_extend_v16qi_v2di,
	gen_vsx_sign_extend_hi_v2di with gen_vsx_sign_extend_v8hi_v2di and
	gen_vsx_sign_extend_si_v2di with gen_vsx_sign_extend_v4si_v2di.

gcc/testsuite/
	PR target/108812
	* gcc.target/powerpc/p9-sign_extend-runnable.c: Set corresponding
	expected vectors for Big Endian.
	* gcc.target/powerpc/int_128bit-runnable.c: Likewise.

1 files changed, 3 insertions, 3 deletions

diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc
index 83c28cd8a..534698e 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -2840,17 +2840,17 @@ lxvrse_expand_builtin (rtx target, insn_code icode, rtx *op,
   if (icode == CODE_FOR_vsx_lxvrbx)
     {
       temp1  = simplify_gen_subreg (V16QImode, tiscratch, TImode, 0);
-      emit_insn (gen_vsx_sign_extend_qi_v2di (discratch, temp1));
+      emit_insn (gen_vsx_sign_extend_v16qi_v2di (discratch, temp1));
     }
   else if (icode == CODE_FOR_vsx_lxvrhx)
     {
       temp1  = simplify_gen_subreg (V8HImode, tiscratch, TImode, 0);
-      emit_insn (gen_vsx_sign_extend_hi_v2di (discratch, temp1));
+      emit_insn (gen_vsx_sign_extend_v8hi_v2di (discratch, temp1));
     }
   else if (icode == CODE_FOR_vsx_lxvrwx)
     {
       temp1  = simplify_gen_subreg (V4SImode, tiscratch, TImode, 0);
-      emit_insn (gen_vsx_sign_extend_si_v2di (discratch, temp1));
+      emit_insn (gen_vsx_sign_extend_v4si_v2di (discratch, temp1));
     }
   else if (icode == CODE_FOR_vsx_lxvrdx)
     discratch = simplify_gen_subreg (V2DImode, tiscratch, TImode, 0);