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authorSegher Boessenkool <segher@kernel.crashing.org>2014-05-08 00:00:58 +0200
committerSegher Boessenkool <segher@gcc.gnu.org>2014-05-08 00:00:58 +0200
commitd839f53b7dfd86250420bce15382c98cbd43b4ec (patch)
treecd8a170e4a1bf065792be21e8461f7608f25a897 /gcc/config/rs6000/power8.md
parentd3b4df0b173c3ad5f1e8f5d9f6a5df3518322129 (diff)
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rs6000: New attributes for load/store: "sign_extend", "update" and "indexed"
The new attributes replace the instruction types *_ext*, *_u, *_ux. This simplifies all code that does not care about the addressing modes, putting the burden on the code that does care (mostly the scheduling descriptions for certain CPUs). It fixes a few minor bugs in the process. The "update" and "indexed" attributes are automatic for any insn that has a MEM as operand 0 or 1. Other insns have to set it manually, if they do not like the default (which is "no"). Insns that are type load/store/fpload/fpstore but have fewer than two operands need to set it too, or the compiler will crash. There are very few of those. This tries not to change semantics anywhere; in particular, the string and multiple instructions set both "update" and "indexed" (although they are neither). From-SVN: r210190
Diffstat (limited to 'gcc/config/rs6000/power8.md')
-rw-r--r--gcc/config/rs6000/power8.md33
1 files changed, 25 insertions, 8 deletions
diff --git a/gcc/config/rs6000/power8.md b/gcc/config/rs6000/power8.md
index b6bb853..7af5eab 100644
--- a/gcc/config/rs6000/power8.md
+++ b/gcc/config/rs6000/power8.md
@@ -80,51 +80,68 @@
; LS Unit
(define_insn_reservation "power8-load" 3
(and (eq_attr "type" "load")
+ (eq_attr "sign_extend" "no")
+ (eq_attr "update" "no")
(eq_attr "cpu" "power8"))
"DU_any_power8,LU_or_LSU_power8")
(define_insn_reservation "power8-load-update" 3
- (and (eq_attr "type" "load_u,load_ux")
+ (and (eq_attr "type" "load")
+ (eq_attr "sign_extend" "no")
+ (eq_attr "update" "yes")
(eq_attr "cpu" "power8"))
"DU_cracked_power8,LU_or_LSU_power8+FXU_power8")
(define_insn_reservation "power8-load-ext" 3
- (and (eq_attr "type" "load_ext")
+ (and (eq_attr "type" "load")
+ (eq_attr "sign_extend" "yes")
+ (eq_attr "update" "no")
(eq_attr "cpu" "power8"))
"DU_cracked_power8,LU_or_LSU_power8,FXU_power8")
(define_insn_reservation "power8-load-ext-update" 3
- (and (eq_attr "type" "load_ext_u,load_ext_ux")
+ (and (eq_attr "type" "load")
+ (eq_attr "sign_extend" "yes")
+ (eq_attr "update" "yes")
(eq_attr "cpu" "power8"))
"DU_both_power8,LU_or_LSU_power8+FXU_power8,FXU_power8")
(define_insn_reservation "power8-fpload" 5
- (and (eq_attr "type" "fpload,vecload")
+ (and (ior (eq_attr "type" "vecload")
+ (and (eq_attr "type" "fpload")
+ (eq_attr "update" "no")))
(eq_attr "cpu" "power8"))
"DU_any_power8,LU_power8")
(define_insn_reservation "power8-fpload-update" 5
- (and (eq_attr "type" "fpload_u,fpload_ux")
+ (and (eq_attr "type" "fpload")
+ (eq_attr "update" "yes")
(eq_attr "cpu" "power8"))
"DU_cracked_power8,LU_power8+FXU_power8")
(define_insn_reservation "power8-store" 5 ; store-forwarding latency
- (and (eq_attr "type" "store,store_u")
+ (and (eq_attr "type" "store")
+ (not (and (eq_attr "update" "yes")
+ (eq_attr "indexed" "yes")))
(eq_attr "cpu" "power8"))
"DU_any_power8,LSU_power8+LU_power8")
(define_insn_reservation "power8-store-update-indexed" 5
- (and (eq_attr "type" "store_ux")
+ (and (eq_attr "type" "store")
+ (eq_attr "update" "yes")
+ (eq_attr "indexed" "yes")
(eq_attr "cpu" "power8"))
"DU_cracked_power8,LSU_power8+LU_power8")
(define_insn_reservation "power8-fpstore" 5
(and (eq_attr "type" "fpstore")
+ (eq_attr "update" "no")
(eq_attr "cpu" "power8"))
"DU_any_power8,LSU_power8+VSU_power8")
(define_insn_reservation "power8-fpstore-update" 5
- (and (eq_attr "type" "fpstore_u,fpstore_ux")
+ (and (eq_attr "type" "fpstore")
+ (eq_attr "update" "yes")
(eq_attr "cpu" "power8"))
"DU_any_power8,LSU_power8+VSU_power8")