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| author | Michael Meissner <meissner@linux.ibm.com> | 2019-07-03 17:42:09 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2019-07-03 17:42:09 +0000 |
| commit | 911c8df0a30913ba6c84b8a65cb338e9c54efeee (patch) | |
| tree | ef66f50fa6ac0ce56655b704e2a3506682740acd /gcc/config/rs6000/altivec.md | |
| parent | e5833b56497c5cf04034ce68d6b9c73c2600158b (diff) | |
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altivec.md (altivec_mov<mode>, [...]): Change the RTL attribute "length" from "4" to "*" to allow the length attribute...
2019-07-03 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/altivec.md (altivec_mov<mode>, VM2 iterator):
Change the RTL attribute "length" from "4" to "*" to allow the
length attribute to be adjusted automatically for prefixed load,
store, and add immediate instructions.
* config/rs6000/rs6000.md (extendhi<mode>2, EXTHI iterator):
Likewise.
(extendsi<mode>2, EXTSI iterator): Likewise.
(movsi_internal1): Likewise.
(movsi_from_sf): Likewise.
(movdi_from_sf_zero_ext): Likewise.
(mov<mode>_internal): Likewise.
(movcc_internal1, QHI iterator): Likewise.
(mov<mode>_softfloat, FMOVE32 iterator): Likewise.
(movsf_from_si): Likewise.
(mov<mode>_hardfloat32, FMOVE64 iterator): Likewise.
(mov<mode>_softfloat64, FMOVE64 iterator): Likewise.
(mov<mode>, FMOVE128 iterator): Likewise.
(movdi_internal64): Likewise.
* config/rs6000/vsx.md (vsx_le_permute_<mode>, VSX_TI iterator):
Likewise.
(vsx_le_undo_permute_<mode>, VSX_TI iterator): Likewise.
(vsx_mov<mode>_64bit, VSX_M iterator): Likewise.
(vsx_mov<mode>_32bit, VSX_M iterator): Likewise.
(vsx_splat_v4sf): Likewise.
From-SVN: r273013
Diffstat (limited to 'gcc/config/rs6000/altivec.md')
| -rw-r--r-- | gcc/config/rs6000/altivec.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index b6a22d9..3a8cd76 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -256,7 +256,7 @@ * return output_vec_const_move (operands); #" [(set_attr "type" "vecstore,vecload,veclogical,store,load,*,veclogical,*,*") - (set_attr "length" "4,4,4,20,20,20,4,8,32")]) + (set_attr "length" "*,*,*,20,20,20,*,8,32")]) ;; Unlike other altivec moves, allow the GPRs, since a normal use of TImode ;; is for unions. However for plain data movement, slightly favor the vector |