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+/* Definitions of target machine for GNU compiler, for ROMP chip.
+   Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+   Contributed by Richard Kenner (kenner@nyu.edu)
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+
+/* Names to predefine in the preprocessor for this target machine.  */
+
+#define CPP_PREDEFINES "-Dibm032 -Dunix"
+
+/* Print subsidiary information on the compiler version in use.  */
+#define TARGET_VERSION ;
+
+/* Add -lfp_p when running with -p or -pg.  */
+#define LIB_SPEC "%{pg:-lfp_p}%{p:-lfp_p} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"
+
+/* Run-time compilation parameters selecting different hardware subsets.  */
+
+/* Flag to generate all multiplies as an in-line sequence of multiply-step
+   insns instead of calling a library routine.  */
+#define TARGET_IN_LINE_MUL (target_flags & 1)
+
+/* Flag to generate padded floating-point data blocks.  Otherwise, we generate
+   them the minimum size.  This trades off execution speed against size.  */
+#define TARGET_FULL_FP_BLOCKS (target_flags & 2)
+
+/* Flag to pass and return floating point values in floating point registers.
+   Since this violates the linkage convention, we feel free to destroy fr2
+   and fr3 on function calls.
+   fr1-fr3 are used to pass the arguments. */
+#define TARGET_FP_REGS (target_flags & 4)
+
+/* Flag to return structures of more than one word in memory.  This is for
+   compatibility with the MetaWare HighC (hc) compiler.  */
+#define TARGET_HC_STRUCT_RETURN (target_flags & 010)
+
+extern int target_flags;
+
+/* Macro to define tables used to set the flags.
+   This is a list in braces of pairs in braces,
+   each pair being { "NAME", VALUE }
+   where VALUE is the bits to set or minus the bits to clear.
+   An empty string NAME is used to identify the default VALUE.  */
+
+#define TARGET_SWITCHES		\
+  { {"in-line-mul", 1},		\
+    {"call-lib-mul", -1},	\
+    {"full-fp-blocks", 2},	\
+    {"minimum-fp-blocks", -2},	\
+    {"fp-arg-in-fpregs", 4},	\
+    {"fp-arg-in-gregs", -4},	\
+    {"hc-struct-return", 010},  \
+    {"nohc-struct-return", - 010}, \
+    { "", TARGET_DEFAULT}}
+
+#define TARGET_DEFAULT 3
+
+/* Define this to change the optimizations peformed by default.  */
+
+#define OPTIMIZATION_OPTIONS(LEVEL) 
+
+/* Define this to modify the options specified by the user.
+
+   On the ROMP, we turn on various flags if optimization is selected.
+   More get turned on if debugging is off.  */
+
+#define OVERRIDE_OPTIONS		\
+{					\
+  if (optimize)				\
+    {					\
+      flag_force_addr = 1;		\
+      flag_force_mem = 1;		\
+      if (write_symbols == NO_DEBUG)	\
+	flag_omit_frame_pointer = 1;	\
+    }					\
+}
+
+/* target machine storage layout */
+
+/* Define this if most significant bit is lowest numbered
+   in instructions that operate on numbered bit-fields. */
+/* That is true on ROMP. */
+#define BITS_BIG_ENDIAN 1
+
+/* Define this if most significant byte of a word is the lowest numbered.  */
+/* That is true on ROMP.  */
+#define BYTES_BIG_ENDIAN 1
+
+/* Define this if most significant word of a multiword number is lowest
+   numbered. 
+
+   For ROMP we can decide arbitrarily since there are no machine instructions
+   for them.  Might as well be consistent with bits and bytes. */
+#define WORDS_BIG_ENDIAN 1
+
+/* number of bits in an addressible storage unit */
+#define BITS_PER_UNIT 8
+
+/* Width in bits of a "word", which is the contents of a machine register.
+   Note that this is not necessarily the width of data type `int';
+   if using 16-bit ints on a 68000, this would still be 32.
+   But on a machine with 16-bit registers, this would be 16.  */
+#define BITS_PER_WORD 32
+
+/* Width of a word, in units (bytes).  */
+#define UNITS_PER_WORD 4
+
+/* Width in bits of a pointer.
+   See also the macro `Pmode' defined below.  */
+#define POINTER_SIZE 32
+
+/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
+#define PARM_BOUNDARY 32
+
+/* Boundary (in *bits*) on which stack pointer should be aligned.  */
+#define STACK_BOUNDARY 32
+
+/* Allocation boundary (in *bits*) for the code of a function.  */
+#define FUNCTION_BOUNDARY 16
+
+/* No data type wants to be aligned rounder than this.  */
+#define BIGGEST_ALIGNMENT 32
+
+/* Alignment of field after `int : 0' in a structure.  */
+#define EMPTY_FIELD_BOUNDARY 32
+
+/* Every structure's size must be a multiple of this.  */
+#define STRUCTURE_SIZE_BOUNDARY 8
+
+/* A bitfield declared as `int' forces `int' alignment for the struct.  */
+#define PCC_BITFIELD_TYPE_MATTERS 1
+
+/* Make strings word-aligned so strcpy from constants will be faster.  */
+#define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
+  (TREE_CODE (EXP) == STRING_CST	\
+   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
+
+/* Make arrays of chars word-aligned for the same reasons.  */
+#define DATA_ALIGNMENT(TYPE, ALIGN)		\
+  (TREE_CODE (TYPE) == ARRAY_TYPE		\
+   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode	\
+   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
+
+/* Define this if move instructions will actually fail to work
+   when given unaligned data.  */
+#define STRICT_ALIGNMENT
+
+/* Standard register usage.  */
+
+/* Number of actual hardware registers.
+   The hardware registers are assigned numbers for the compiler
+   from 0 to just below FIRST_PSEUDO_REGISTER.
+   All registers that the compiler knows about must be given numbers,
+   even those that are not normally considered general registers.
+
+   ROMP has 16 fullword registers and 8 floating point registers.
+
+   In addition, the difference between the frame and argument pointers is
+   a function of the number of registers saved, so we need to have a register
+   to use for AP that will later be eliminated in favor of sp or fp.  This is
+   a normal register, but it is fixed.  */
+
+#define FIRST_PSEUDO_REGISTER 25
+
+/* 1 for registers that have pervasive standard uses
+   and are not available for the register allocator.
+
+   On ROMP, r1 is used for the stack and r14 is used for a
+   data area pointer.
+
+   HACK WARNING:  On the RT, there is a bug in code generation for
+   the MC68881 when the first and third operands are the same floating-point
+   register.  See the definition of the FINAL_PRESCAN_INSN macro for details.
+   Here we need to reserve fr0 for this purpose.  */
+#define FIXED_REGISTERS  \
+ {0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,	\
+  1,							\
+  1, 0, 0, 0, 0, 0, 0, 0}
+
+/* 1 for registers not available across function calls.
+   These must include the FIXED_REGISTERS and also any
+   registers that can be used without being saved.
+   The latter must include the registers where values are returned
+   and the register where structure-value addresses are passed.
+   Aside from that, you can include as many other registers as you like.  */
+#define CALL_USED_REGISTERS				\
+ {1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,	\
+  1,							\
+  1, 1, 0, 0, 0, 0, 0, 0}
+
+/* List the order in which to allocate registers.  Each register must be
+   listed once, even those in FIXED_REGISTERS.
+
+   We allocate in the following order:
+	fr0, fr1	(not saved)
+	fr2 ... fr6
+	fr7		(more expensive for some FPA's)
+	r0		(not saved and won't conflict with parameter register)
+	r4, r3, r2	(not saved, highest used first to make less conflict)
+	r5		(not saved, but forces r6 to be saved if DI/DFmode)
+	r15, r14, r13, r12, r11, r10, r9, r8, r7, r6 (less to save)
+	r1, ap 			*/
+
+#define REG_ALLOC_ORDER		\
+  {17, 18,			\
+   19, 20, 21, 22, 23,		\
+   24,				\
+   0,				\
+   4, 3, 2,			\
+   5,				\
+   15, 14, 13, 12, 11, 10,	\
+   9, 8, 7, 6, 			\
+   1, 16}
+
+/* True if register is floating-point.  */
+#define FP_REGNO_P(N) ((N) >= 17)
+
+/* Return number of consecutive hard regs needed starting at reg REGNO
+   to hold something of mode MODE.
+   This is ordinarily the length in words of a value of mode MODE
+   but can be less for certain modes in special long registers.
+
+   On ROMP, ordinary registers hold 32 bits worth;
+   a single floating point register is always enough for
+   anything that can be stored in them at all.  */
+#define HARD_REGNO_NREGS(REGNO, MODE)   \
+  (FP_REGNO_P (REGNO) ? GET_MODE_NUNITS (MODE)	\
+   : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
+
+/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
+   On ROMP, the cpu registers can hold any mode but the float registers
+   can hold only floating point. */
+#define HARD_REGNO_MODE_OK(REGNO, MODE) \
+  (! FP_REGNO_P (REGNO) || GET_MODE_CLASS (MODE) == MODE_FLOAT	\
+   || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)
+
+/* Value is 1 if it is a good idea to tie two pseudo registers
+   when one has mode MODE1 and one has mode MODE2.
+   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
+   for any hard reg, then this must be 0 for correct output.  */
+#define MODES_TIEABLE_P(MODE1, MODE2) \
+  ((GET_MODE_CLASS (MODE1) == MODE_FLOAT		\
+    || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT)	\
+   == (GET_MODE_CLASS (MODE2) == MODE_FLOAT		\
+       || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
+
+/* A C expression returning the cost of moving data from a register of class
+   CLASS1 to one of CLASS2.
+
+   On the ROMP, access to floating-point registers is expensive (even between
+   two FP regs.)  */
+#define REGISTER_MOVE_COST(CLASS1, CLASS2)	\
+  (2 + 10 * ((CLASS1) == FP_REGS) + 10 * (CLASS2 == FP_REGS))
+
+/* Specify the registers used for certain standard purposes.
+   The values of these macros are register numbers.  */
+
+/* ROMP pc isn't overloaded on a register that the compiler knows about.  */
+/* #define PC_REGNUM  */
+
+/* Register to use for pushing function arguments.  */
+#define STACK_POINTER_REGNUM 1
+
+/* Base register for access to local variables of the function.  */
+#define FRAME_POINTER_REGNUM 13
+
+/* Value should be nonzero if functions must have frame pointers.
+   Zero means the frame pointer need not be set up (and parms
+   may be accessed via the stack pointer) in functions that seem suitable.
+   This is computed in `reload', in reload1.c.  */
+#define FRAME_POINTER_REQUIRED 0
+
+/* Base register for access to arguments of the function.  */
+#define ARG_POINTER_REGNUM 16
+
+/* Place to put static chain when calling a function that requires it.  */
+#define STATIC_CHAIN							\
+  gen_rtx (MEM, Pmode, gen_rtx (PLUS, Pmode, stack_pointer_rtx,		\
+				gen_rtx (CONST_INT, VOIDmode, -36)))
+
+/* Place where static chain is found upon entry to routine.  */
+#define STATIC_CHAIN_INCOMING						\
+  gen_rtx (MEM, Pmode, gen_rtx (PLUS, Pmode, arg_pointer_rtx,		\
+				gen_rtx (CONST_INT, VOIDmode, -20)))
+
+/* Place that structure value return address is placed.
+
+   On the ROMP, it is passed as an extra parameter.  */
+#define STRUCT_VALUE	0
+
+/* Define the classes of registers for register constraints in the
+   machine description.  Also define ranges of constants.
+
+   One of the classes must always be named ALL_REGS and include all hard regs.
+   If there is more than one class, another class must be named NO_REGS
+   and contain no registers.
+
+   The name GENERAL_REGS must be the name of a class (or an alias for
+   another name such as ALL_REGS).  This is the class of registers
+   that is allowed by "g" or "r" in a register constraint.
+   Also, registers outside this class are allocated only when
+   instructions express preferences for them.
+
+   The classes must be numbered in nondecreasing order; that is,
+   a larger-numbered class must never be contained completely
+   in a smaller-numbered class.
+
+   For any two classes, it is very desirable that there be another
+   class that represents their union.  */
+   
+/* The ROMP has two types of registers, general and floating-point.
+
+   However, r0 is special in that it cannot be used as a base register.
+   So make a class for registers valid as base registers.
+
+   For floating-point support, add classes that just consist of r0 and
+   r15, respectively.  */
+
+enum reg_class { NO_REGS, R0_REGS, R15_REGS, BASE_REGS, GENERAL_REGS,
+		 FP_REGS, ALL_REGS, LIM_REG_CLASSES };
+
+#define N_REG_CLASSES (int) LIM_REG_CLASSES
+
+/* Give names of register classes as strings for dump file.   */
+
+#define REG_CLASS_NAMES \
+ {"NO_REGS", "R0_REGS", "R15_REGS", "BASE_REGS", "GENERAL_REGS", \
+  "FP_REGS", "ALL_REGS" }
+
+/* Define which registers fit in which classes.
+   This is an initializer for a vector of HARD_REG_SET
+   of length N_REG_CLASSES.  */
+
+#define REG_CLASS_CONTENTS {0, 0x00001, 0x08000, 0x1fffe, 0x1ffff,  \
+			    0x1fe0000, 0x1ffffff }
+
+/* The same information, inverted:
+   Return the class number of the smallest class containing
+   reg number REGNO.  This could be a conditional expression
+   or could index an array.  */
+
+#define REGNO_REG_CLASS(REGNO) \
+ ((REGNO) == 0 ? GENERAL_REGS : FP_REGNO_P (REGNO) ? FP_REGS : BASE_REGS)
+
+/* The class value for index registers, and the one for base regs.  */
+#define INDEX_REG_CLASS BASE_REGS
+#define BASE_REG_CLASS BASE_REGS
+
+/* Get reg_class from a letter such as appears in the machine description.  */
+
+#define REG_CLASS_FROM_LETTER(C) \
+  ((C) == 'f' ? FP_REGS		\
+   : (C) == 'b' ? BASE_REGS	\
+   : (C) == 'z' ? R0_REGS	\
+   : (C) == 't' ? R15_REGS	\
+   : NO_REGS)
+
+/* The letters I, J, K, L, M, N, and P in a register constraint string
+   can be used to stand for particular ranges of immediate operands.
+   This macro defines what the ranges are.
+   C is the letter, and VALUE is a constant value.
+   Return 1 if VALUE is in the range specified by C.
+
+   `I' is constants less than 16
+   `J' is negative constants greater than -16
+   `K' is the range for a normal D insn.
+   `L' is a constant with only the low-order 16 bits set
+   `M' is a constant with only the high-order 16 bits set
+   `N' is a single-bit constant
+   `O' is a constant with either the high-order or low-order 16 bits all ones
+   `P' is the complement of a single-bit constant
+  */
+
+#define CONST_OK_FOR_LETTER_P(VALUE, C)  		   \
+   ( (C) == 'I' ? (unsigned) (VALUE) < 0x10		   \
+   : (C) == 'J' ? (VALUE) < 0 && (VALUE) > -16		   \
+   : (C) == 'K' ? (unsigned) ((VALUE) + 0x8000) < 0x10000  \
+   : (C) == 'L' ? ((VALUE) & 0xffff0000) == 0		   \
+   : (C) == 'M' ? ((VALUE) & 0xffff) == 0		   \
+   : (C) == 'N' ? exact_log2 (VALUE) >= 0		   \
+   : (C) == 'O' ? ((VALUE) & 0xffff) == 0xffff		   \
+		  || ((VALUE) & 0xffff0000) == 0xffff0000  \
+   : (C) == 'P' ? exact_log2 (~ (VALUE)) >= 0		   \
+   : 0)
+
+/* Similar, but for floating constants, and defining letters G and H.
+   Here VALUE is the CONST_DOUBLE rtx itself.
+   No floating-point constants on ROMP.  */
+
+#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)  0
+
+/* Optional extra constraints for this machine.
+
+   For the ROMP, `Q' means that this is a memory operand but not a symbolic
+   memory operand.  Note that an unassigned pseudo register is such a
+   memory operand.  If register allocation has not been done, we reject
+   pseudos, since we assume (hope) that they will get hard registers.
+
+   `R' means that this is a constant pool reference to the current function.
+   This is just r14 and so can be treated as a register.  We bother with this
+   just in move insns as that is the only place it is likely to occur.
+
+   `S' means that this is the address of a constant pool location.  This is
+   equal to r14 plus a constant.  We also only check for this in move insns. */
+
+#define EXTRA_CONSTRAINT(OP, C)				\
+  ((C) == 'Q' ?						\
+   ((GET_CODE (OP) == REG				\
+     && REGNO (OP) >= FIRST_PSEUDO_REGISTER		\
+     && reg_renumber != 0				\
+     && reg_renumber[REGNO (OP)] < 0)			\
+    || (memory_operand (OP, VOIDmode)			\
+        && ! symbolic_memory_operand (OP, VOIDmode)))	\
+   : (C) == 'R' ? current_function_operand (OP, VOIDmode) \
+   : (C) == 'S' ? constant_pool_address_operand (OP, VOIDmode) \
+   : 0)
+
+/* Given an rtx X being reloaded into a reg required to be
+   in class CLASS, return the class of reg to actually use.
+   In general this is just CLASS; but on some machines
+   in some cases it is preferable to use a more restrictive class.
+
+   For the ROMP, if X is a memory reference that involves a symbol,
+   we must use a BASE_REGS register instead of GENERAL_REGS
+   to do the reload. The argument of MEM be either REG, PLUS, or SYMBOL_REF
+   to be valid, so we assume that this is the case.
+
+   Also, if X is an integer class, ensure that floating-point registers
+   aren't used.  */
+
+#define PREFERRED_RELOAD_CLASS(X,CLASS)					\
+  ((CLASS) == FP_REGS && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT	\
+   ? GENERAL_REGS :							\
+   (CLASS) != GENERAL_REGS ? (CLASS) :					\
+   GET_CODE (X) != MEM ? GENERAL_REGS :					\
+   GET_CODE (XEXP (X, 0)) == SYMBOL_REF ? BASE_REGS :			\
+   GET_CODE (XEXP (X, 0)) == LABEL_REF ? BASE_REGS :			\
+   GET_CODE (XEXP (X, 0)) == CONST ? BASE_REGS :			\
+   GET_CODE (XEXP (X, 0)) == REG ? GENERAL_REGS :			\
+   GET_CODE (XEXP (X, 0)) != PLUS ? GENERAL_REGS :			\
+   GET_CODE (XEXP (XEXP (X, 0), 1)) == SYMBOL_REF ? BASE_REGS :		\
+   GET_CODE (XEXP (XEXP (X, 0), 1)) == LABEL_REF ? BASE_REGS :		\
+   GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST ? BASE_REGS : GENERAL_REGS)
+
+/* Return the register class of a scratch register needed to store into
+   OUT from a register of class CLASS in MODE.  
+
+   On the ROMP, we cannot store into a symbolic memory address from an
+   integer register; we need a BASE_REGS register as a scratch to do it.  */
+
+#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
+  (GET_MODE_CLASS (MODE) == MODE_INT && symbolic_memory_operand (OUT, MODE) \
+   ? BASE_REGS : NO_REGS)
+
+/* Return the maximum number of consecutive registers
+   needed to represent mode MODE in a register of class CLASS.
+
+   On ROMP, this is the size of MODE in words,
+   except in the FP regs, where a single reg is always enough.  */
+#define CLASS_MAX_NREGS(CLASS, MODE)	\
+ ((CLASS) == FP_REGS ? 1			\
+  : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
+
+/* Stack layout; function entry, exit and calling.  */
+
+/* Define this if pushing a word on the stack
+   makes the stack pointer a smaller address.  */
+#define STACK_GROWS_DOWNWARD
+
+/* Define this if the nominal address of the stack frame
+   is at the high-address end of the local variables;
+   that is, each additional local variable allocated
+   goes at a more negative offset in the frame.  */
+#define FRAME_GROWS_DOWNWARD
+
+/* Offset within stack frame to start allocating local variables at.
+   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
+   first local allocated.  Otherwise, it is the offset to the BEGINNING
+   of the first local allocated.
+   On the ROMP, if we set the frame pointer to 15 words below the highest
+   address of the highest local variable, the first 16 words will be
+   addressable via D-short insns. */
+#define STARTING_FRAME_OFFSET 64
+
+/* If we generate an insn to push BYTES bytes,
+   this says how many the stack pointer really advances by.
+   On ROMP, don't define this because there are no push insns.  */
+/*  #define PUSH_ROUNDING(BYTES) */
+
+/* Offset of first parameter from the argument pointer register value.
+   On the ROMP, we define the argument pointer to the start of the argument
+   area.  */
+#define FIRST_PARM_OFFSET(FNDECL) 0
+
+/* Define this if stack space is still allocated for a parameter passed
+   in a register.  The value is the number of bytes.  */
+#define REG_PARM_STACK_SPACE(FNDECL) 16
+
+/* This is the difference between the logical top of stack and the actual sp.
+
+   For the ROMP, sp points past the words allocated for the first four outgoing
+   arguments (they are part of the callee's frame).  */
+#define STACK_POINTER_OFFSET -16
+
+/* Define this if the maximum size of all the outgoing args is to be
+   accumulated and pushed during the prologue.  The amount can be
+   found in the variable current_function_outgoing_args_size.  */
+#define ACCUMULATE_OUTGOING_ARGS
+
+/* Value is the number of bytes of arguments automatically
+   popped when returning from a subroutine call.
+   FUNTYPE is the data type of the function (as a tree),
+   or for a library call it is an identifier node for the subroutine name.
+   SIZE is the number of bytes of arguments passed on the stack.  */
+
+#define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0
+
+/* Define how to find the value returned by a function.
+   VALTYPE is the data type of the value (as a tree).
+   If the precise function being called is known, FUNC is its FUNCTION_DECL;
+   otherwise, FUNC is 0.
+
+   On ROMP the value is found in r2, unless the machine specific option
+   fp-arg-in-fpregs is selected, in which case FP return values are in fr1 */
+
+#define FUNCTION_VALUE(VALTYPE, FUNC)	\
+  gen_rtx (REG, TYPE_MODE (VALTYPE),	\
+	   (TARGET_FP_REGS &&		\
+	    GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT) ? 18 : 2)
+
+/* Define how to find the value returned by a library function
+   assuming the value has mode MODE.  */
+
+#define LIBCALL_VALUE(MODE)  gen_rtx (REG, MODE, 2)
+
+/* The definition of this macro implies that there are cases where
+   a scalar value cannot be returned in registers.
+
+   For the ROMP, if compatibility with HC is required, anything of
+   type DImode is returned in memory.  */
+
+#define RETURN_IN_MEMORY(type) \
+  (TARGET_HC_STRUCT_RETURN && TYPE_MODE (type) == DImode)
+
+/* 1 if N is a possible register number for a function value
+   as seen by the caller.
+
+   On ROMP, r2 is the only register thus used unless fp values are to be
+   returned in fp regs, in which case fr1 is also used.  */
+
+#define FUNCTION_VALUE_REGNO_P(N)  ((N) == 2 || ((N) == 18 && TARGET_FP_REGS))
+
+/* 1 if N is a possible register number for function argument passing.
+   On ROMP, these are r2-r5 (and fr1-fr4 if fp regs are used).  */
+
+#define FUNCTION_ARG_REGNO_P(N)	\
+  (((N) <= 5 && (N) >= 2) || (TARGET_FP_REGS && (N) > 17 && (N) < 21))
+
+/* Define a data type for recording info about an argument list
+   during the scan of that argument list.  This data type should
+   hold all necessary information about the function itself
+   and about the args processed so far, enough to enable macros
+   such as FUNCTION_ARG to determine where the next arg should go.
+
+   On the ROMP, this is a structure.  The first word is the number of
+   words of (integer only if -mfp-arg-in-fpregs is specified) arguments
+   scanned so far (including the invisible argument, if any, which holds
+   the structure-value-address).  The second word hold the corresponding
+   value for floating-point arguments, except that both single and double
+   count as one register.  */
+
+struct rt_cargs {int gregs, fregs; };
+#define CUMULATIVE_ARGS struct rt_cargs 
+
+#define USE_FP_REG(MODE,CUM)					\
+  (TARGET_FP_REGS && GET_MODE_CLASS (MODE) == MODE_FLOAT	\
+   && (CUM).fregs < 3)
+
+/* Define intermediate macro to compute the size (in registers) of an argument
+   for the ROMP.  */
+
+#define ROMP_ARG_SIZE(MODE, TYPE, NAMED)				\
+(! (NAMED) ? 0								\
+ : (MODE) != BLKmode							\
+ ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD 	\
+ : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
+
+/* Initialize a variable CUM of type CUMULATIVE_ARGS
+   for a call to a function whose data type is FNTYPE.
+   For a library call, FNTYPE is 0.
+
+   On ROMP, the offset normally starts at 0, but starts at 4 bytes
+   when the function gets a structure-value-address as an
+   invisible first argument.  */
+
+#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME)	\
+  (CUM).gregs = 0,				\
+  (CUM).fregs = 0
+
+/* Update the data in CUM to advance over an argument
+   of mode MODE and data type TYPE.
+   (TYPE is null for libcalls where that information may not be available.)  */
+
+#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
+{ if (NAMED)						\
+    {							\
+      if (USE_FP_REG(MODE, CUM))			\
+	(CUM).fregs++;					\
+      else						\
+	(CUM).gregs += ROMP_ARG_SIZE (MODE, TYPE, NAMED); \
+    }							\
+}
+
+/* Determine where to put an argument to a function.
+   Value is zero to push the argument on the stack,
+   or a hard register in which to store the argument.
+
+   MODE is the argument's machine mode.
+   TYPE is the data type of the argument (as a tree).
+    This is null for libcalls where that information may
+    not be available.
+   CUM is a variable of type CUMULATIVE_ARGS which gives info about
+    the preceding args and about the function being called.
+   NAMED is nonzero if this argument is a named parameter
+    (otherwise it is an extra parameter matching an ellipsis).
+
+   On ROMP the first four words of args are normally in registers
+   and the rest are pushed.  */
+
+#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED)				\
+  (! (NAMED) ? 0							\
+  : USE_FP_REG(MODE,CUM) ? gen_rtx(REG, (MODE),(CUM.fregs) + 17)	\
+  : (CUM).gregs < 4 ? gen_rtx(REG, (MODE), 2 + (CUM).gregs) : 0)
+
+/* For an arg passed partly in registers and partly in memory,
+   this is the number of registers used.
+   For args passed entirely in registers or entirely in memory, zero.  */
+
+#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED)		\
+  (! (NAMED) ? 0							\
+   : USE_FP_REG(MODE,CUM) ? 0						\
+   : (((CUM).gregs < 4							\
+       && 4 < ((CUM).gregs + ROMP_ARG_SIZE (MODE, TYPE, NAMED)))	\
+      ? 4 - (CUM).gregs : 0))
+
+/* Perform any needed actions needed for a function that is receiving a
+   variable number of arguments. 
+
+   CUM is as above.
+
+   MODE and TYPE are the mode and type of the current parameter.
+
+   PRETEND_SIZE is a variable that should be set to the amount of stack
+   that must be pushed by the prolog to pretend that our caller pushed
+   it.
+
+   Normally, this macro will push all remaining incoming registers on the
+   stack and set PRETEND_SIZE to the length of the registers pushed.  */
+
+#define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL)	\
+{ if (TARGET_FP_REGS)							\
+    error ("can't have varargs with -mfp-arg-in-fp-regs");		\
+  else if ((CUM).gregs < 4)						\
+    {									\
+      int first_reg_offset = (CUM).gregs;				\
+									\
+      if (MUST_PASS_IN_STACK (MODE, TYPE))				\
+	first_reg_offset += ROMP_ARG_SIZE (TYPE_MODE (TYPE), TYPE, 1);	\
+									\
+      if (first_reg_offset > 4)						\
+	first_reg_offset = 4;						\
+									\
+      if (! NO_RTL && first_reg_offset != 4)				\
+	move_block_from_reg						\
+	  (2 + first_reg_offset,					\
+	   gen_rtx (MEM, BLKmode,					\
+		    plus_constant (virtual_incoming_args_rtx,		\
+				   first_reg_offset * 4)), 		\
+	   4 - first_reg_offset);					\
+      PRETEND_SIZE = (4 - first_reg_offset) * UNITS_PER_WORD;		\
+    }									\
+}
+
+/* This macro produces the initial definition of a function name.
+   On the ROMP, we need to place an extra '.' in the function name.  */
+
+#define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL)	\
+{ if (TREE_PUBLIC(DECL))				\
+    fprintf (FILE, "\t.globl _.%s\n", NAME);		\
+  fprintf (FILE, "_.%s:\n", NAME);			\
+}
+
+/* This macro is used to output the start of the data area.
+
+   On the ROMP, the _name is a pointer to the data area.  At that
+   location is the address of _.name, which is really the name of
+   the function.  We need to set all this up here.
+
+   The global declaration of the data area, if needed, is done in 
+   `assemble_function', where it thinks it is globalizing the function
+   itself.  */
+
+#define ASM_OUTPUT_POOL_PROLOGUE(FILE, NAME, DECL, SIZE)	\
+{ extern int data_offset;					\
+  data_section ();						\
+  fprintf (FILE, "\t.align 2\n");				\
+  ASM_OUTPUT_LABEL (FILE, NAME);				\
+  fprintf (FILE, "\t.long _.%s, 0, ", NAME);			\
+  if (current_function_calls_alloca)				\
+    fprintf (FILE, "0x%x\n",					\
+	     0xf6900000 + current_function_outgoing_args_size); \
+  else								\
+    fprintf (FILE, "0\n");					\
+  data_offset = ((SIZE) + 12 + 3) / 4;				\
+}
+
+/* Select section for constant in constant pool.
+
+   On ROMP, all constants are in the data area.  */
+
+#define SELECT_RTX_SECTION(MODE, X)	data_section ()
+
+/* This macro generates the assembly code for function entry.
+   FILE is a stdio stream to output the code to.
+   SIZE is an int: how many units of temporary storage to allocate.
+   Refer to the array `regs_ever_live' to determine which registers
+   to save; `regs_ever_live[I]' is nonzero if register number I
+   is ever used in the function.  This macro is responsible for
+   knowing which registers should not be saved even if used.  */
+
+#define FUNCTION_PROLOGUE(FILE, SIZE) output_prolog (FILE, SIZE)
+
+/* Output assembler code to FILE to increment profiler label # LABELNO
+   for profiling a function entry.  */
+
+#define FUNCTION_PROFILER(FILE, LABELNO)	\
+  fprintf(FILE, "\tcas r0,r15,r0\n\tbali r15,mcount\n");
+
+/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
+   the stack pointer does not matter.  The value is tested only in
+   functions that have frame pointers.
+   No definition is equivalent to always zero.  */
+/* #define EXIT_IGNORE_STACK	1	*/
+
+/* This macro generates the assembly code for function exit,
+   on machines that need it.  If FUNCTION_EPILOGUE is not defined
+   then individual return instructions are generated for each
+   return statement.  Args are same as for FUNCTION_PROLOGUE.
+
+   The function epilogue should not depend on the current stack pointer!
+   It should use the frame pointer only.  This is mandatory because
+   of alloca; we also take advantage of it to omit stack adjustments
+   before returning.  */
+
+#define FUNCTION_EPILOGUE(FILE, SIZE) output_epilog (FILE, SIZE)
+
+/* Output assembler code for a block containing the constant parts
+   of a trampoline, leaving space for the variable parts.
+
+   The trampoline should set the static chain pointer to value placed
+   into the trampoline and should branch to the specified routine.
+
+   On the ROMP, we have a problem.  There are no free registers to use
+   to construct the static chain and function addresses.  Hence we use
+   the following kludge:  r15 (the return address) is first saved in mq.
+   Then we use r15 to form the function address.  We then branch to the
+   function and restore r15 in the delay slot.  This makes it appear that
+   the function was called directly from the caller.
+
+   (Note that the function address built is actually that of the data block.
+   This is passed in r0 and the actual routine address is loaded into r15.)
+
+   In addition, note that the address of the "called function", in this case
+   the trampoline, is actually the address of the data area.  So we need to
+   make a fake data area that will contain the address of the trampoline.
+   Note that this must be defined as two half-words, since the trampoline
+   template (as opposed to the trampoline on the stack) is only half-word
+   aligned.  */
+
+#define TRAMPOLINE_TEMPLATE(FILE)	\
+{					\
+  fprintf (FILE, "\t.short 0,0\n");	\
+  fprintf (FILE, "\tcau r0,0(r0)\n");	\
+  fprintf (FILE, "\toil r0,r0,0\n");	\
+  fprintf (FILE, "\tmts r10,r15\n");	\
+  fprintf (FILE, "\tst r0,-36(r1)\n");	\
+  fprintf (FILE, "\tcau r15,0(r0)\n");	\
+  fprintf (FILE, "\toil r15,r15,0\n");	\
+  fprintf (FILE, "\tcas r0,r15,r0\n");	\
+  fprintf (FILE, "\tls r15,0(r15)\n");	\
+  fprintf (FILE, "\tbrx r15\n");	\
+  fprintf (FILE, "\tmfs r10,r15\n");	\
+}
+
+/* Length in units of the trampoline for entering a nested function.  */
+
+#define TRAMPOLINE_SIZE    36
+
+/* Emit RTL insns to initialize the variable parts of a trampoline.
+   FNADDR is an RTX for the address of the function's pure code.
+   CXT is an RTX for the static chain value for the function.
+
+   On the RT, the static chain and function addresses are written in
+   two 16-bit sections.
+
+   We also need to write the address of the first instruction in
+   the trampoline into the first word of the trampoline to simulate a
+   data area.  */
+
+#define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT)		\
+{								\
+  rtx _addr, _temp;						\
+  rtx _val;							\
+								\
+  _temp = expand_binop (SImode, add_optab, ADDR,		\
+			gen_rtx (CONST_INT, VOIDmode, 4),	\
+			0, 1, OPTAB_LIB_WIDEN);			\
+  emit_move_insn (gen_rtx (MEM, SImode,				\
+			   memory_address (SImode, ADDR)), _temp); \
+								\
+  _val = force_reg (SImode, CXT);				\
+  _addr = memory_address (HImode, plus_constant (ADDR, 10));	\
+  emit_move_insn (gen_rtx (MEM, HImode, _addr),			\
+		  gen_lowpart (HImode, _val));			\
+  _temp = expand_shift (RSHIFT_EXPR, SImode, _val,		\
+			build_int_2 (16, 0), 0, 1);		\
+  _addr = memory_address (HImode, plus_constant (ADDR, 6));	\
+  emit_move_insn (gen_rtx (MEM, HImode, _addr),			\
+		  gen_lowpart (HImode, _temp));			\
+								\
+  _val = force_reg (SImode, FNADDR);				\
+  _addr = memory_address (HImode, plus_constant (ADDR, 24));	\
+  emit_move_insn (gen_rtx (MEM, HImode, _addr),			\
+		  gen_lowpart (HImode, _val));			\
+  _temp = expand_shift (RSHIFT_EXPR, SImode, _val,		\
+			build_int_2 (16, 0), 0, 1);		\
+  _addr = memory_address (HImode, plus_constant (ADDR, 20));	\
+  emit_move_insn (gen_rtx (MEM, HImode, _addr),			\
+		  gen_lowpart (HImode, _temp));			\
+								\
+}
+
+/* Definitions for register eliminations.
+
+   We have two registers that can be eliminated on the ROMP.  First, the
+   frame pointer register can often be eliminated in favor of the stack
+   pointer register.  Secondly, the argument pointer register can always be
+   eliminated; it is replaced with either the stack or frame pointer.
+
+   In addition, we use the elimination mechanism to see if r14 is needed.
+   Initially we assume that it isn't.  If it is, we spill it.  This is done
+   by making it an eliminable register.  It doesn't matter what we replace
+   it with, since it will never occur in the rtl at this point.  */
+
+/* This is an array of structures.  Each structure initializes one pair
+   of eliminable registers.  The "from" register number is given first,
+   followed by "to".  Eliminations of the same "from" register are listed
+   in order of preference.  */
+#define ELIMINABLE_REGS				\
+{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},	\
+ { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},	\
+ { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},	\
+ { 14, 0}}
+
+/* Given FROM and TO register numbers, say whether this elimination is allowed.
+   Frame pointer elimination is automatically handled.
+
+   For the ROMP, if frame pointer elimination is being done, we would like to
+   convert ap into fp, not sp.
+
+   We need r14 if various conditions (tested in romp_using_r14) are true.
+
+   All other eliminations are valid.  */
+#define CAN_ELIMINATE(FROM, TO)					\
+ ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM	\
+  ? ! frame_pointer_needed					\
+  : (FROM) == 14 ? ! romp_using_r14 ()				\
+  : 1)
+
+/* Define the offset between two registers, one to be eliminated, and the other
+   its replacement, at the start of a routine.  */
+#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)			\
+{ if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)	\
+    {									\
+      if (romp_pushes_stack ())						\
+	(OFFSET) = ((get_frame_size () - 64)				\
+		    + current_function_outgoing_args_size);		\
+      else								\
+	(OFFSET) = - (romp_sa_size () + 64);				\
+    }									\
+  else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
+    (OFFSET) = romp_sa_size () - 16 + 64;				\
+  else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
+    {									\
+      if (romp_pushes_stack ())						\
+	(OFFSET) = (get_frame_size () + (romp_sa_size () - 16)		\
+		    + current_function_outgoing_args_size);		\
+      else								\
+	(OFFSET) = -16;							\
+    }									\
+  else if ((FROM) == 14)						\
+    (OFFSET) = 0;							\
+  else									\
+    abort ();								\
+}
+
+/* Addressing modes, and classification of registers for them.  */
+
+/* #define HAVE_POST_INCREMENT */
+/* #define HAVE_POST_DECREMENT */
+
+/* #define HAVE_PRE_DECREMENT */
+/* #define HAVE_PRE_INCREMENT */
+
+/* Macros to check register numbers against specific register classes.  */
+
+/* These assume that REGNO is a hard or pseudo reg number.
+   They give nonzero only if REGNO is a hard reg of the suitable class
+   or a pseudo reg currently allocated to a suitable hard reg.
+   Since they use reg_renumber, they are safe only once reg_renumber
+   has been allocated, which happens in local-alloc.c.  */
+
+#define REGNO_OK_FOR_INDEX_P(REGNO) 0
+#define REGNO_OK_FOR_BASE_P(REGNO)				\
+((REGNO) < FIRST_PSEUDO_REGISTER				\
+ ? (REGNO) < 16 && (REGNO) != 0 && (REGNO) != 16		\
+ : (reg_renumber[REGNO] < 16 && reg_renumber[REGNO] >= 0	\
+    && reg_renumber[REGNO] != 16))
+
+/* Maximum number of registers that can appear in a valid memory address.  */
+
+#define MAX_REGS_PER_ADDRESS 1
+
+/* Recognize any constant value that is a valid address.  */
+
+#define CONSTANT_ADDRESS_P(X)  CONSTANT_P (X)
+
+/* Nonzero if the constant value X is a legitimate general operand.
+   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
+
+   On the ROMP, there is a bit of a hack here.  Basically, we wish to
+   only issue instructions that are not `as' macros.  However, in the
+   case of `get', `load', and `store', if the operand is a relocatable
+   symbol (possibly +/- an integer), there is no way to express the
+   resulting split-relocation except with the macro.  Therefore, allow
+   either a constant valid in a normal (sign-extended) D-format insn or
+   a relocatable expression.
+
+   Also, for DFmode and DImode, we must ensure that both words are
+   addressable.
+
+   We define two macros: The first is given an offset (0 or 4) and indicates
+   that the operand is a CONST_INT that is valid for that offset.  The second
+   indicates a valid non-CONST_INT constant.  */
+
+#define LEGITIMATE_ADDRESS_INTEGER_P(X,OFFSET)				\
+  (GET_CODE (X) == CONST_INT						\
+   && (unsigned) (INTVAL (X) + (OFFSET) + 0x8000) < 0x10000)
+
+#define LEGITIMATE_ADDRESS_CONSTANT_P(X)				\
+ (GET_CODE (X) == SYMBOL_REF						\
+  || GET_CODE (X) == LABEL_REF						\
+  || (GET_CODE (X) == CONST						\
+      && (GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF		\
+          || GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF)		\
+      && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT))
+
+/* Include all constant integers and constant double, but exclude 
+   SYMBOL_REFs that are to be obtained from the data area (see below).  */
+#define LEGITIMATE_CONSTANT_P(X)		\
+  ((LEGITIMATE_ADDRESS_CONSTANT_P (X)		\
+    || GET_CODE (X) == CONST_INT		\
+    || GET_CODE (X) == CONST_DOUBLE)		\
+   && ! (GET_CODE (X) == SYMBOL_REF && (X)->integrated))
+
+/* For no good reason, we do the same as the other RT compilers and load
+   the addresses of data areas for a function from our data area.  That means
+   that we need to mark such SYMBOL_REFs.  We do so here.  */
+#define ENCODE_SEGMENT_INFO(DECL)			\
+  if (TREE_CODE (TREE_TYPE (DECL)) == FUNCTION_TYPE)	\
+    XEXP (DECL_RTL (DECL), 0)->integrated = 1;
+
+/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
+   and check its validity for a certain class.
+   We have two alternate definitions for each of them.
+   The usual definition accepts all pseudo regs; the other rejects
+   them unless they have been allocated suitable hard regs.
+   The symbol REG_OK_STRICT causes the latter definition to be used.
+
+   Most source files want to accept pseudo regs in the hope that
+   they will get allocated to the class that the insn wants them to be in.
+   Source files for reload pass need to be strict.
+   After reload, it makes no difference, since pseudo regs have
+   been eliminated by then.  */
+
+#ifndef REG_OK_STRICT
+
+/* Nonzero if X is a hard reg that can be used as an index
+   or if it is a pseudo reg.  */
+#define REG_OK_FOR_INDEX_P(X) 0
+/* Nonzero if X is a hard reg that can be used as a base reg
+   or if it is a pseudo reg.  */
+#define REG_OK_FOR_BASE_P(X)		\
+  (REGNO (X) != 0 && (REGNO (X) < 17 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
+
+#else
+
+/* Nonzero if X is a hard reg that can be used as an index.  */
+#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
+/* Nonzero if X is a hard reg that can be used as a base reg.  */
+#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
+
+#endif
+
+/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
+   that is a valid memory address for an instruction.
+   The MODE argument is the machine mode for the MEM expression
+   that wants to use this address.
+
+   On the ROMP, a legitimate address is either a legitimate constant,
+   a register plus a legitimate constant, or a register.  See the
+   discussion at the LEGITIMATE_ADDRESS_CONSTANT_P macro.  */
+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)				\
+{ if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))			\
+    goto ADDR;								\
+  if (GET_CODE (X) != CONST_INT && LEGITIMATE_ADDRESS_CONSTANT_P (X))	\
+    goto ADDR;								\
+  if (GET_CODE (X) == PLUS						\
+      && GET_CODE (XEXP (X, 0)) == REG					\
+      && REG_OK_FOR_BASE_P (XEXP (X, 0))				\
+      && LEGITIMATE_ADDRESS_CONSTANT_P (XEXP (X, 1)))			\
+	goto ADDR;							\
+  if (GET_CODE (X) == PLUS						\
+      && GET_CODE (XEXP (X, 0)) == REG					\
+      && REG_OK_FOR_BASE_P (XEXP (X, 0))				\
+      && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 0)			\
+      && (((MODE) != DFmode && (MODE) != DImode)			\
+	  || (LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 4))))		\
+	goto ADDR;							\
+}
+
+/* Try machine-dependent ways of modifying an illegitimate address
+   to be legitimate.  If we find one, return the new, valid address.
+   This macro is used in only one place: `memory_address' in explow.c.
+
+   OLDX is the address as it was before break_out_memory_refs was called.
+   In some cases it is useful to look at this to decide what needs to be done.
+
+   MODE and WIN are passed so that this macro can use
+   GO_IF_LEGITIMATE_ADDRESS.
+
+   It is always safe for this macro to do nothing.  It exists to recognize
+   opportunities to optimize the output.
+
+   On ROMP, check for the sum of a register with a constant
+   integer that is out of range.  If so, generate code to add the
+   constant with the low-order 16 bits masked to the register and force
+   this result into another register (this can be done with `cau').
+   Then generate an address of REG+(CONST&0xffff), allowing for the 
+   possibility of bit 16 being a one.
+
+   If the register is not OK for a base register, abort.  */
+
+#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)			\
+{ if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG	\
+    && GET_CODE (XEXP (X, 1)) == CONST_INT			\
+    && (unsigned) (INTVAL (XEXP (X, 1)) + 0x8000) >= 0x10000)	\
+    { int high_int, low_int;					\
+      if (! REG_OK_FOR_BASE_P (XEXP (X, 0)))			\
+	abort ();						\
+      high_int = INTVAL (XEXP (X, 1)) >> 16;			\
+      low_int = INTVAL (XEXP (X, 1)) & 0xffff;			\
+      if (low_int & 0x8000)					\
+	high_int += 1, low_int |= 0xffff0000;			\
+      (X) = gen_rtx (PLUS, SImode,				\
+		     force_operand				\
+		     	(gen_rtx (PLUS, SImode, XEXP (X, 0), \
+				  gen_rtx (CONST_INT, VOIDmode, \
+						      high_int << 16)), 0),\
+		     gen_rtx (CONST_INT, VOIDmode, low_int));	\
+    }								\
+}
+
+/* Go to LABEL if ADDR (a legitimate address expression)
+   has an effect that depends on the machine mode it is used for.
+
+   On the ROMP this is true only if the address is valid with a zero offset
+   but not with an offset of four (this means it cannot be used as an
+   address for DImode or DFmode).  Since we know it is valid, we just check
+   for an address that is not valid with an offset of four.  */
+
+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)		\
+{ if (GET_CODE (ADDR) == PLUS					\
+      && ! LEGITIMATE_ADDRESS_CONSTANT_P (XEXP (ADDR, 1))	\
+      && ! LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), 4))	\
+    goto LABEL;							\
+}
+
+/* Define this if some processing needs to be done immediately before
+   emitting code for an insn.
+
+   This is used on the ROMP, to compensate for a bug in the floating-point
+   code.  When a floating-point operation is done with the first and third
+   operands both the same floating-point register, it will generate bad code
+   for the MC68881.  So we must detect this.  If it occurs, we patch the 
+   first operand to be fr0 and insert a move insn to move it to the desired
+   destination.  */
+#define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS)			\
+  { rtx op0, op1, op2, operation, tem;					\
+    if (NOPERANDS >= 3	&& get_attr_type (INSN) == TYPE_FP)		\
+      {									\
+	op0 = OPERANDS[0];						\
+	operation = OPERANDS[1];					\
+	if (float_conversion (operation, VOIDmode))			\
+	  operation = XEXP (operation, 0);				\
+        if (float_binary (operation, VOIDmode))				\
+	  {								\
+	    op1 = XEXP (operation, 0), op2 = XEXP (operation, 1);	\
+	    if (float_conversion (op1, VOIDmode))			\
+	      op1 = XEXP (op1, 0);					\
+	    if (float_conversion (op2, VOIDmode))			\
+	      op2 = XEXP (op2, 0);					\
+	    if (rtx_equal_p (op0, op2)					\
+		&& (GET_CODE (operation) == PLUS			\
+		    || GET_CODE (operation) == MULT))			\
+	      tem = op1, op1 = op2, op2 = tem;				\
+	    if (GET_CODE (op0) == REG && FP_REGNO_P (REGNO (op0))	\
+		&& GET_CODE (op2) == REG && FP_REGNO_P (REGNO (op2))	\
+		&& REGNO (op0) == REGNO (op2))				\
+	      {								\
+		tem = gen_rtx (REG, GET_MODE (op0), 17);		\
+		emit_insn_after (gen_move_insn (op0, tem), INSN);	\
+		SET_DEST (XVECEXP (PATTERN (INSN), 0, 0)) = tem; 	\
+		OPERANDS[0] = tem;					\
+	      }								\
+	  }								\
+      }									\
+  }
+
+/* Specify the machine mode that this machine uses
+   for the index in the tablejump instruction.  */
+#define CASE_VECTOR_MODE SImode
+
+/* Define this if the tablejump instruction expects the table
+   to contain offsets from the address of the table.
+   Do not define this if the table should contain absolute addresses.  */
+/* #define CASE_VECTOR_PC_RELATIVE */
+
+/* Specify the tree operation to be used to convert reals to integers.  */
+#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
+
+/* This is the kind of divide that is easiest to do in the general case.  */
+#define EASY_DIV_EXPR TRUNC_DIV_EXPR
+
+/* Define this as 1 if `char' should by default be signed; else as 0.  */
+#define DEFAULT_SIGNED_CHAR 0
+
+/* This flag, if defined, says the same insns that convert to a signed fixnum
+   also convert validly to an unsigned one.
+
+   We actually lie a bit here as overflow conditions are different.  But
+   they aren't being checked anyway.  */
+
+#define FIXUNS_TRUNC_LIKE_FIX_TRUNC
+
+/* Max number of bytes we can move from memory to memory
+   in one reasonably fast instruction.  */
+#define MOVE_MAX 4
+
+/* Nonzero if access to memory by bytes is no faster than for words.
+   Also non-zero if doing byte operations (specifically shifts) in registers
+   is undesirable.  */
+#define SLOW_BYTE_ACCESS 1
+
+/* Define if normal loads of shorter-than-word items from memory clears
+   the rest of the bigs in the register.  */
+#define BYTE_LOADS_ZERO_EXTEND
+
+/* This is BSD, so it wants DBX format.  */
+#define DBX_DEBUGGING_INFO
+
+/* We don't have GAS for the RT yet, so don't write out special
+   .stabs in cc1plus.  */
+   
+#define FASCIST_ASSEMBLER
+
+/* Do not break .stabs pseudos into continuations.  */
+#define DBX_CONTIN_LENGTH 0
+
+/* Don't try to use the `x' type-cross-reference character in DBX data.
+   Also has the consequence of putting each struct, union or enum
+   into a separate .stabs, containing only cross-refs to the others.  */
+#define DBX_NO_XREFS
+
+/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
+   is done just by pretending it is already truncated.  */
+#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
+
+/* Specify the machine mode that pointers have.
+   After generation of rtl, the compiler makes no further distinction
+   between pointers and any other objects of this machine mode.  */
+#define Pmode SImode
+
+/* Mode of a function address in a call instruction (for indexing purposes).
+
+   Doesn't matter on ROMP.  */
+#define FUNCTION_MODE SImode
+
+/* Define this if addresses of constant functions
+   shouldn't be put through pseudo regs where they can be cse'd.
+   Desirable on machines where ordinary constants are expensive
+   but a CALL with constant address is cheap.  */
+#define NO_FUNCTION_CSE
+
+/* Define this if shift instructions ignore all but the low-order
+   few bits. */
+#define SHIFT_COUNT_TRUNCATED
+
+/* Compute the cost of computing a constant rtl expression RTX
+   whose rtx-code is CODE.  The body of this macro is a portion
+   of a switch statement.  If the code is computed here,
+   return it with a return statement.  Otherwise, break from the switch.  */
+
+#define CONST_COSTS(RTX,CODE) \
+  case CONST_INT:						\
+    return 0;							\
+  case CONST:							\
+  case LABEL_REF:						\
+  case SYMBOL_REF:						\
+  case CONST_DOUBLE:						\
+    return COSTS_N_INSNS (2);
+
+/* Provide the costs of a rtl expression.  This is in the body of a
+   switch on CODE. 
+
+   References to our own data area are really references to r14, so they
+   are very cheap.  Multiples and divides are very expensive.  */
+
+#define RTX_COSTS(X,CODE)				\
+  case MEM:						\
+    return current_function_operand (X, Pmode) ? 0 : COSTS_N_INSNS (2);	\
+  case MULT:						\
+    return TARGET_IN_LINE_MUL ? COSTS_N_INSNS (19) : COSTS_N_INSNS (25); \
+  case DIV:						\
+  case UDIV:						\
+  case MOD:						\
+  case UMOD:						\
+    return COSTS_N_INSNS (45);
+
+/* Compute the cost of an address.  This is meant to approximate the size
+   and/or execution delay of an insn using that address.  If the cost is
+   approximated by the RTL complexity, including CONST_COSTS above, as
+   is usually the case for CISC machines, this macro should not be defined.
+   For aggressively RISCy machines, only one insn format is allowed, so
+   this macro should be a constant.  The value of this macro only matters
+   for valid addresses.
+
+   For the ROMP, everything is cost 0 except for addresses involving
+   symbolic constants, which are cost 1.  */
+
+#define ADDRESS_COST(RTX)				\
+  ((GET_CODE (RTX) == SYMBOL_REF			\
+    && ! CONSTANT_POOL_ADDRESS_P (RTX))			\
+   || GET_CODE (RTX) == LABEL_REF			\
+   || (GET_CODE (RTX) == CONST				\
+       && ! constant_pool_address_operand (RTX, Pmode))	\
+   || (GET_CODE (RTX) == PLUS				\
+       && ((GET_CODE (XEXP (RTX, 1)) == SYMBOL_REF	\
+	    && ! CONSTANT_POOL_ADDRESS_P (XEXP (RTX, 0))) \
+	   || GET_CODE (XEXP (RTX, 1)) == LABEL_REF	\
+	   || GET_CODE (XEXP (RTX, 1)) == CONST)))
+
+/* Adjust the length of an INSN.  LENGTH is the currently-computed length and
+   should be adjusted to reflect any required changes.  This macro is used when
+   there is some systematic length adjustment required that would be difficult
+   to express in the length attribute.
+
+   On the ROMP, there are two adjustments:  First, a 2-byte insn in the delay
+   slot of a CALL (including floating-point operations) actually takes four
+   bytes.  Second, we have to make the worst-case alignment assumption for
+   address vectors.  */
+
+#define ADJUST_INSN_LENGTH(X,LENGTH)					\
+  if (GET_CODE (X) == INSN && GET_CODE (PATTERN (X)) == SEQUENCE	\
+      && GET_CODE (XVECEXP (PATTERN (X), 0, 0)) != JUMP_INSN		\
+      && get_attr_length (XVECEXP (PATTERN (X), 0, 1)) == 2)		\
+    (LENGTH) += 2;							\
+  else if (GET_CODE (X) == JUMP_INSN && GET_CODE (PATTERN (X)) == ADDR_VEC) \
+    (LENGTH) += 2;
+
+/* Tell final.c how to eliminate redundant test instructions.  */
+
+/* Here we define machine-dependent flags and fields in cc_status
+   (see `conditions.h').  */
+
+/* Set if condition code (really not-Z) is stored in `test bit'.  */
+#define CC_IN_TB	 01000
+
+/* Set if condition code is set by an unsigned compare. */
+#define	CC_UNSIGNED        02000
+
+/* Store in cc_status the expressions
+   that the condition codes will describe
+   after execution of an instruction whose pattern is EXP.
+   Do not alter them if the instruction would not alter the cc's.  */
+
+#define NOTICE_UPDATE_CC(BODY,INSN) \
+  update_cc (BODY, INSN)
+
+/* Control the assembler format that we output.  */
+
+/* Output at beginning of assembler file.  */
+
+#define ASM_FILE_START(FILE)				\
+{ extern char *version_string;				\
+  fprintf (FILE, "\t.globl .oVncs\n\t.set .oVncs,0\n") ; \
+  fprintf (FILE, "\t.globl .oVgcc%s\n\t.set .oVgcc%s,0\n", \
+	   version_string, version_string);		\
+}
+
+/* Output to assembler file text saying following lines
+   may contain character constants, extra white space, comments, etc.  */
+
+#define ASM_APP_ON ""
+
+/* Output to assembler file text saying following lines
+   no longer contain unusual constructs.  */
+
+#define ASM_APP_OFF ""
+
+/* Output before instructions and read-only data.  */
+
+#define TEXT_SECTION_ASM_OP "\t.text"
+
+/* Output before writable data.  */
+
+#define DATA_SECTION_ASM_OP "\t.data"
+
+/* How to refer to registers in assembler output.
+   This sequence is indexed by compiler's hard-register-number (see above).  */
+
+#define REGISTER_NAMES \
+{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",	\
+ "r10", "r11", "r12", "r13", "r14", "r15", "ap",		\
+ "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7" }
+
+/* How to renumber registers for dbx and gdb.  */
+
+#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
+
+/* This is how to output the definition of a user-level label named NAME,
+   such as the label on a static function or variable NAME.  */
+
+#define ASM_OUTPUT_LABEL(FILE,NAME)	\
+  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
+
+/* This is how to output a command to make the user-level label named NAME
+   defined for reference from other files.  */
+
+#define ASM_GLOBALIZE_LABEL(FILE,NAME)	\
+  do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
+
+/* This is how to output a reference to a user-level label named NAME.
+   `assemble_name' uses this.  */
+
+#define ASM_OUTPUT_LABELREF(FILE,NAME)	\
+  fprintf (FILE, "_%s", NAME)
+
+/* This is how to output an internal numbered label where
+   PREFIX is the class of label and NUM is the number within the class.  */
+
+#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
+  fprintf (FILE, "%s%d:\n", PREFIX, NUM)
+
+/* This is how to output a label for a jump table.  Arguments are the same as
+   for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is
+   passed. */
+
+#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN)	\
+{ ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }
+
+/* This is how to store into the string LABEL
+   the symbol_ref name of an internal numbered label where
+   PREFIX is the class of label and NUM is the number within the class.
+   This is suitable for output with `assemble_name'.  */
+
+#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
+  sprintf (LABEL, "*%s%d", PREFIX, NUM)
+
+/* This is how to output an assembler line defining a `double' constant.  */
+
+#define ASM_OUTPUT_DOUBLE(FILE,VALUE)		\
+  fprintf (FILE, "\t.double 0d%.20e\n", (VALUE))
+
+/* This is how to output an assembler line defining a `float' constant.
+
+   WARNING:  Believe it or not, the ROMP assembler has a bug in its
+   handling of single-precision floating-point values making it impossible
+   to output such values in the expected way.  Therefore, it must be output
+   in hex.  THIS WILL NOT WORK IF CROSS-COMPILING FROM A MACHINE THAT DOES
+   NOT USE IEEE-FORMAT FLOATING-POINT, but there is nothing that can be done
+   about it short of fixing the assembler.  */
+
+#define ASM_OUTPUT_FLOAT(FILE,VALUE)		\
+  do { union { int i; float f; } u_i_f;		\
+       u_i_f.f = (VALUE);			\
+       fprintf (FILE, "\t.long 0x%x\n", u_i_f.i);\
+     } while (0)
+
+/* This is how to output an assembler line defining an `int' constant.  */
+
+#define ASM_OUTPUT_INT(FILE,VALUE)  \
+( fprintf (FILE, "\t.long "),			\
+  output_addr_const (FILE, (VALUE)),		\
+  fprintf (FILE, "\n"))
+
+/* Likewise for `char' and `short' constants.  */
+
+#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
+( fprintf (FILE, "\t.short "),			\
+  output_addr_const (FILE, (VALUE)),		\
+  fprintf (FILE, "\n"))
+
+#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
+( fprintf (FILE, "\t.byte "),			\
+  output_addr_const (FILE, (VALUE)),		\
+  fprintf (FILE, "\n"))
+
+/* This is how to output an assembler line for a numeric constant byte.  */
+
+#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
+  fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
+
+/* This is how to output code to push a register on the stack.
+   It need not be very fast code.  */
+
+#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
+  fprintf (FILE, "\tsis r1,4\n\tsts %s,0(r1)\n", reg_names[REGNO])
+
+/* This is how to output an insn to pop a register from the stack.
+   It need not be very fast code.  */
+
+#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
+  fprintf (FILE, "\tls r1,0(r1)\n\tais r1,4\n", reg_names[REGNO])
+
+/* This is how to output an element of a case-vector that is absolute.  */
+
+#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
+  fprintf (FILE, "\t.long L%d\n", VALUE)
+
+/* This is how to output an element of a case-vector that is relative.
+   (ROMP does not use such vectors,
+   but we must define this macro anyway.)  */
+
+#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL)  abort ()
+
+/* This is how to output an assembler line
+   that says to advance the location counter
+   to a multiple of 2**LOG bytes.  */
+
+#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
+  if ((LOG) != 0)			\
+    fprintf (FILE, "\t.align %d\n", (LOG))
+
+#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
+  fprintf (FILE, "\t.space %d\n", (SIZE))
+
+/* This says how to output an assembler line
+   to define a global common symbol.  */
+
+#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
+( fputs (".comm ", (FILE)),			\
+  assemble_name ((FILE), (NAME)),		\
+  fprintf ((FILE), ",%d\n", (SIZE)))
+
+/* This says how to output an assembler line
+   to define a local common symbol.  */
+
+#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED)	\
+( fputs (".lcomm ", (FILE)),				\
+  assemble_name ((FILE), (NAME)),			\
+  fprintf ((FILE), ",%d\n", (SIZE)))
+
+/* Store in OUTPUT a string (made with alloca) containing
+   an assembler-name for a local static variable named NAME.
+   LABELNO is an integer which is different for each call.  */
+
+#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
+( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
+  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
+
+/* Define the parentheses used to group arithmetic operations
+   in assembler code.  */
+
+#define ASM_OPEN_PAREN "("
+#define ASM_CLOSE_PAREN ")"
+
+/* Define results of standard character escape sequences.  */
+#define TARGET_BELL 007
+#define TARGET_BS 010
+#define TARGET_TAB 011
+#define TARGET_NEWLINE 012
+#define TARGET_VT 013
+#define TARGET_FF 014
+#define TARGET_CR 015
+
+/* Print operand X (an rtx) in assembler syntax to file FILE.
+   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
+   For `%' followed by punctuation, CODE is the punctuation and X is null.  */
+
+#define PRINT_OPERAND(FILE, X, CODE)  print_operand (FILE, X, CODE)
+
+/* Define which CODE values are valid.  */
+
+#define PRINT_OPERAND_PUNCT_VALID_P(CODE)	\
+  ((CODE) == '.' || (CODE) == '#')
+
+/* Print a memory address as an operand to reference that memory location.  */
+
+#define PRINT_OPERAND_ADDRESS(FILE, ADDR)			\
+{ register rtx addr = ADDR;					\
+  register rtx base = 0, offset = addr;				\
+  if (GET_CODE (addr) == REG)					\
+    base = addr, offset = const0_rtx;				\
+  else if (GET_CODE (addr) == PLUS				\
+	   && GET_CODE (XEXP (addr, 0)) == REG)			\
+    base = XEXP (addr, 0), offset = XEXP (addr, 1);		\
+  else if (GET_CODE (addr) == SYMBOL_REF			\
+	   && CONSTANT_POOL_ADDRESS_P (addr))			\
+    {								\
+      offset = gen_rtx (CONST_INT, VOIDmode, get_pool_offset (addr) + 12);  \
+      base = gen_rtx (REG, SImode, 14);				\
+    }								\
+  else if (GET_CODE (addr) == CONST				\
+	   && GET_CODE (XEXP (addr, 0)) == PLUS			\
+	   && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT	\
+	   && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF	\
+	   && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addr, 0), 0))) \
+    {								\
+      offset = plus_constant (XEXP (XEXP (addr, 0), 1),		\
+			      (get_pool_offset (XEXP (XEXP (addr, 0), 0)) \
+			       + 12));				\
+      base = gen_rtx (REG, SImode, 14);				\
+    }								\
+  output_addr_const (FILE, offset);				\
+  if (base)							\
+    fprintf (FILE, "(%s)", reg_names [REGNO (base)]);		\
+}
+
+/* Define the codes that are matched by predicates in aux-output.c.  */
+
+#define PREDICATE_CODES \
+  {"zero_memory_operand", {SUBREG, MEM}},			\
+  {"short_memory_operand", {SUBREG, MEM}},			\
+  {"symbolic_memory_operand", {SUBREG, MEM}},			\
+  {"current_function_operand", {MEM}},				\
+  {"constant_pool_address_operand", {SUBREG, CONST}},		\
+  {"romp_symbolic_operand", {LABEL_REF, SYMBOL_REF, CONST}},	\
+  {"constant_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST, CONST_INT}}, \
+  {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}},		\
+  {"reg_or_any_cint_operand", {SUBREG, REG, CONST_INT}},	\
+  {"short_cint_operand", {CONST_INT}},				\
+  {"reg_or_D_operand", {SUBREG, REG, CONST_INT}},		\
+  {"reg_or_add_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF,	\
+			  PLUS, CONST, CONST_INT}}, 		\
+  {"reg_or_and_operand", {SUBREG, REG, CONST_INT}},		\
+  {"reg_or_mem_operand", {SUBREG, REG, MEM}},			\
+  {"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}},		\
+  {"romp_operand", {SUBREG, MEM, REG, CONST_INT, CONST, LABEL_REF, \
+		    SYMBOL_REF, CONST_DOUBLE}},			\
+  {"reg_0_operand", {REG}},					\
+  {"reg_15_operand", {REG}},					\
+  {"float_binary", {PLUS, MINUS, MULT, DIV}},			\
+  {"float_unary", {NEG, ABS}},					\
+  {"float_conversion", {FLOAT_TRUNCATE, FLOAT_EXTEND, FLOAT, FIX}},
+
+/* Define functions defined in aux-output.c and used in templates.  */
+
+extern char *output_in_line_mul ();
+extern char *output_fpop ();
diff --git a/gcc/config/romp/romp.md b/gcc/config/romp/romp.md
new file mode 100644
index 0000000..6d732fe
--- /dev/null
+++ b/gcc/config/romp/romp.md
@@ -0,0 +1,2728 @@
+;;- Machine description for ROMP chip for GNU C compiler
+;;   Copyright (C) 1988, 1991 Free Software Foundation, Inc.
+;;   Contributed by Richard Kenner (kenner@nyu.edu)
+
+;; This file is part of GNU CC.
+
+;; GNU CC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+
+;; GNU CC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GNU CC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+
+
+;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
+
+;; Define the attributes for the ROMP.
+
+;; Insn type.  Used to default other attribute values.
+
+(define_attr "type"
+  "branch,return,fp,load,loadz,store,call,address,arith,compare,multi,misc"
+  (const_string "arith"))
+
+;; Length in bytes.
+
+(define_attr "length" ""
+  (cond [(eq_attr "type" "branch")
+	 (if_then_else (and (ge (minus (pc) (match_dup 0))
+				(const_int -256))
+			    (le (minus (pc) (match_dup 0))
+				(const_int 254)))
+		       (const_int 2)
+		       (const_int 4))
+	 (eq_attr "type" "return")	(const_int 2)
+	 (eq_attr "type" "fp")		(const_int 10)
+	 (eq_attr "type" "call")	(const_int 4)
+	 (eq_attr "type" "load")
+	   (cond [(match_operand 1 "short_memory_operand" "") (const_int 2)
+		  (match_operand 1 "symbolic_memory_operand" "") (const_int 8)]
+		 (const_int 4))
+         (eq_attr "type" "loadz")
+	   (cond [(match_operand 1 "zero_memory_operand" "") (const_int 2)
+		  (match_operand 1 "symbolic_memory_operand" "") (const_int 8)]
+		 (const_string "4"))
+	 (eq_attr "type" "store")
+	   (cond [(match_operand 0 "short_memory_operand" "") (const_int 2)
+		  (match_operand 0 "symbolic_memory_operand" "") (const_int 8)]
+		 (const_int 4))]
+	(const_int 4)))
+
+;; Whether insn can be placed in a delay slot.
+
+(define_attr "in_delay_slot" "yes,no" 
+  (cond [(eq_attr "length" "8,10,38")			(const_string "no")
+	 (eq_attr "type" "branch,return,call,multi")	(const_string "no")]
+	(const_string "yes")))
+
+;; Whether insn needs a delay slot.
+(define_attr "needs_delay_slot" "yes,no"
+  (if_then_else (eq_attr "type" "branch,return,call")
+		(const_string "yes") (const_string "no")))
+
+;; What insn does to the condition code.
+
+(define_attr "cc"
+  "clobber,none,sets,change0,copy1to0,compare,tbit"
+  (cond [(eq_attr "type" "load,loadz")		(const_string "change0")
+	 (eq_attr "type" "store")		(const_string "none")
+	 (eq_attr "type" "fp,call")		(const_string "clobber")
+	 (eq_attr "type" "branch,return")	(const_string "none")
+	 (eq_attr "type" "address")		(const_string "change0")
+	 (eq_attr "type" "compare")		(const_string "compare")
+	 (eq_attr "type" "arith")		(const_string "sets")]
+	(const_string "clobber")))
+
+;; Define attributes for `asm' insns.
+
+(define_asm_attributes [(set_attr "type" "misc")
+			(set_attr "length" "8")
+			(set_attr "in_delay_slot" "no")
+			(set_attr "cc" "clobber")])
+
+;; Define the delay slot requirements for branches and calls.  We don't have
+;; any annulled insns.
+;;
+(define_delay (eq_attr "needs_delay_slot" "yes")
+  [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
+
+;; We cannot give a floating-point comparison a delay slot, even though it
+;; could make use of it.  This is because it would confuse next_cc0_user
+;; to do so.  Other fp insns can't get a delay slow because they set their
+;; result and use their input after the delay slot insn is executed.  This
+;; isn't what reorg.c expects.  
+
+;; Define load & store delays.  These were obtained by measurements done by
+;; jfc@athena.mit.edu.
+;;
+;; In general, the memory unit can support at most two simultaneous operations.
+;;
+;; Loads take 5 cycles to return the data and can be pipelined up to the
+;; limit of two simultaneous operations.
+(define_function_unit "memory" 1 2 (eq_attr "type" "load,loadz") 5 0)
+
+;; Stores do not return data, but tie up the memory unit for 2 cycles if the
+;; next insn is also a store.
+(define_function_unit "memory" 1 2 (eq_attr "type" "store") 1 2
+  [(eq_attr "type" "store")])
+
+;; Move word instructions.
+;;
+;; If destination is memory but source is not register, force source to
+;; register.
+;;
+;; If source is a constant that is too large to load in a single insn, build
+;; it in two pieces.
+;;
+;; If destination is memory and source is a register, a temporary register
+;; will be needed.  In that case, make a PARALLEL of the SET and a
+;; CLOBBER of a SCRATCH to allocate the required temporary.
+;;
+;; This temporary is ACTUALLY only needed when the destination is a
+;; relocatable expression.  For generating RTL, however, we always
+;; place the CLOBBER.  In insns where it is not needed, the SCRATCH will
+;; not be allocated to a register.
+;;
+;; Also, avoid creating pseudo-registers or SCRATCH rtx's during reload as
+;; they will not be correctly handled.  We never need pseudos for that
+;; case anyway.
+;;
+;; We do not use DEFINE_SPLIT for loading constants because the number
+;; of cases in the resulting unsplit insn would be too high to deal
+;; with practically.
+(define_expand "movsi"
+  [(set (match_operand:SI 0 "general_operand" "")
+	(match_operand:SI 1 "general_operand" ""))]
+  ""
+  "
+{ rtx op0 = operands[0];
+  rtx op1 = operands[1];
+
+  if (GET_CODE (op1) == REG && REGNO (op1) == 16)
+    DONE;
+
+  if (GET_CODE (op0) == REG && REGNO (op0) == 16)
+    DONE;
+
+  if (GET_CODE (op0) == MEM && ! reload_in_progress)
+    {
+      emit_insn (gen_storesi (operands[0], force_reg (SImode, operands[1])));
+      DONE;
+    }
+  else if (GET_CODE (op1) == CONST_INT)
+    {
+      int const_val = INTVAL (op1);
+
+      /* Try a number of cases to see how to best load the constant.  */
+      if ((const_val & 0xffff) == 0
+	  || (const_val & 0xffff0000) == 0
+	  || (unsigned) (const_val + 0x8000) < 0x10000)
+	/* Can do this in one insn, so generate it.  */
+	;
+      else if (((- const_val) & 0xffff) == 0
+	       || ((- const_val) & 0xffff0000) == 0
+	       || (unsigned) ((- const_val) + 0x8000) < 0x10000)
+	{
+	  /* Can do this by loading the negative constant and then negating. */
+	  emit_move_insn (operands[0],
+			  gen_rtx (CONST_INT, VOIDmode, - const_val));
+	  emit_insn (gen_negsi2 (operands[0], operands[0]));
+	  DONE;
+	}
+      else
+	/* Do this the long way.  */
+	{
+	  unsigned int high_part = const_val & 0xffff0000;
+	  unsigned int low_part = const_val & 0xffff;
+	  int i;
+
+	  if (low_part >= 0x10 && exact_log2 (low_part) >= 0)
+	    i = high_part, high_part = low_part, low_part = i;
+
+	  emit_move_insn (operands[0],
+			  gen_rtx (CONST_INT, VOIDmode, low_part));
+	  emit_insn (gen_iorsi3 (operands[0], operands[0],
+				 gen_rtx (CONST_INT, VOIDmode, high_part)));
+	  DONE;
+	}
+    }
+}")
+
+;; Move from a symbolic memory location to a register is special.  In this
+;; case, we know in advance that the register cannot be r0, so we can improve
+;; register allocation by treating it separately.
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=b")
+	(match_operand:SI 1 "symbolic_memory_operand" "m"))]
+  ""
+  "load %0,%1"
+  [(set_attr "type" "load")])
+
+;; Generic single-word move insn.  We avoid the case where the destination is
+;; a symbolic address, as that needs a temporary register.
+
+(define_insn ""
+  [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,r,r,r,b,Q")
+	(match_operand:SI 1 "romp_operand" "rR,I,K,L,M,S,s,Q,m,r"))]
+  "register_operand (operands[0], SImode)
+   || register_operand (operands[1], SImode)"
+  "@
+   cas %0,%1,r0
+   lis %0,%1
+   cal %0,%1(r0)
+   cal16 %0,%1(r0)
+   cau %0,%H1(r0)
+   ail %0,r14,%C1
+   get %0,$%1
+   l%M1 %0,%1
+   load %0,%1
+   st%M0 %1,%0"
+  [(set_attr "type" "address,address,address,address,address,arith,misc,load,load,store")
+   (set_attr "length" "2,2,4,4,4,4,8,*,*,*")])
+
+(define_insn "storesi"
+  [(set (match_operand:SI 0 "memory_operand" "=Q,m")
+	(match_operand:SI 1 "register_operand" "r,r"))
+   (clobber (match_scratch:SI 2 "=X,&b"))]
+  ""
+  "@
+   st%M0 %1,%0
+   store %1,%0,%2"
+  [(set_attr "type" "store")])
+
+;; This pattern is used by reload when we store into a symbolic address.  It
+;; provides the temporary register required.  This pattern is only used
+;; when SECONDARY_OUTPUT_RELOAD_CLASS returns something other than
+;; NO_REGS, so we need not have any predicates here.
+
+(define_expand "reload_outsi"
+  [(set (match_operand:SI 0 "symbolic_memory_operand" "=m")
+	(match_operand:SI 1 "" "r"))
+   (match_operand:SI 2 "" "=&b")]
+  ""
+  "")
+
+;; Now do the same for the QI move instructions.
+(define_expand "movqi"
+  [(set (match_operand:QI 0 "general_operand" "")
+	(match_operand:QI 1 "general_operand" ""))]
+  ""
+  "
+{ rtx op0 = operands[0];
+
+  if (GET_CODE (op0) == MEM && ! reload_in_progress)
+    {
+      emit_insn (gen_storeqi (operands[0], force_reg (QImode, operands[1])));
+      DONE;
+    }
+}")
+
+(define_insn ""
+  [(set (match_operand:QI 0 "register_operand" "=b")
+	(match_operand:QI 1 "symbolic_memory_operand" "m"))]
+  "" 
+  "loadc %0,%1"
+  [(set_attr "type" "load")])
+
+(define_insn ""
+  [(set (match_operand:QI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,b,Q")
+	(match_operand:QI 1 "romp_operand" "r,I,n,s,Q,m,r"))]
+  "register_operand (operands[0], QImode)
+   || register_operand (operands[1], QImode)"
+  "@
+   cas %0,%1,r0
+   lis %0,%1
+   cal %0,%L1(r0)
+   get %0,$%1
+   lc%M1 %0,%1
+   loadc %0,%1
+   stc%M0 %1,%0"
+  [(set_attr "type" "address,address,address,misc,load,load,store")
+   (set_attr "length" "2,2,4,8,*,*,*")])
+
+(define_insn "storeqi"
+  [(set (match_operand:QI 0 "memory_operand" "=Q,m")
+	(match_operand:QI 1 "register_operand" "r,r"))
+   (clobber (match_scratch:SI 2 "=X,&b"))]
+  ""
+  "@
+   stc%M0 %1,%0
+   storec %1,%0,%2"
+  [(set_attr "type" "store")])
+
+(define_expand "reload_outqi"
+  [(set (match_operand:QI 0 "symbolic_memory_operand" "=m")
+	(match_operand:QI 1 "" "r"))
+   (match_operand:SI 2 "" "=&b")]
+  ""
+  "")
+
+;; Finally, the HI instructions.
+(define_expand "movhi"
+  [(set (match_operand:HI 0 "general_operand" "")
+	(match_operand:HI 1 "general_operand" ""))]
+  ""
+  "
+{ rtx op0 = operands[0];
+
+  if (GET_CODE (op0) == MEM && ! reload_in_progress)
+    {
+      emit_insn (gen_storehi (operands[0], force_reg (HImode, operands[1])));
+      DONE;
+    }
+}")
+
+(define_insn ""
+  [(set (match_operand:HI 0 "register_operand" "=b")
+	(match_operand:HI 1 "symbolic_memory_operand" "m"))]
+  ""
+  "loadha %0,%1"
+  [(set_attr "type" "load")])
+
+(define_insn ""
+  [(set (match_operand:HI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,b,Q")
+	(match_operand:HI 1 "romp_operand" "r,I,n,s,Q,m,r"))]
+  "register_operand (operands[0], HImode)
+   || register_operand (operands[1], HImode)"
+  "@
+   cas %0,%1,r0
+   lis %0,%1
+   cal %0,%L1(r0)
+   get %0,$%1
+   lh%N1 %0,%1
+   loadh %0,%1
+   sth%M0 %1,%0"
+  [(set_attr "type" "address,address,address,misc,loadz,loadz,store")
+   (set_attr "length" "2,2,4,8,*,*,*")])
+
+(define_insn "storehi"
+  [(set (match_operand:HI 0 "memory_operand" "=Q,m")
+	(match_operand:HI 1 "register_operand" "r,r"))
+   (clobber (match_scratch:SI 2 "=X,&b"))]
+  ""
+  "@
+   sth%M0 %1,%0
+   storeh %1,%0,%2"
+  [(set_attr "type" "store")])
+
+(define_expand "reload_outhi"
+  [(set (match_operand:HI 0 "symbolic_memory_operand" "=m")
+	(match_operand:HI 1 "" "r"))
+   (match_operand:SI 2 "" "=&b")]
+  ""
+  "")
+
+;; For DI move, if we have a constant, break the operation apart into
+;; two SImode moves because the optimizer may be able to do a better job
+;; with the resulting code.
+;;
+;; For memory stores, make the required pseudo for a temporary in case we
+;; are storing into an absolute address.
+;;
+;; We need to be careful about the cases where the output is a register that is
+;; the second register of the input.
+
+(define_expand "movdi"
+  [(set (match_operand:DI 0 "general_operand" "")
+	(match_operand:DI 1 "general_operand" ""))]
+  ""
+  "
+{ rtx op0 = operands[0];
+  rtx op1 = operands[1];
+ 
+  if (CONSTANT_P (op1))
+    {
+      rtx insns;
+
+      start_sequence ();
+      emit_move_insn (operand_subword (op0, 0, 1, DImode),
+		      operand_subword (op1, 0, 1, DImode));
+      emit_move_insn (operand_subword (op0, 1, 1, DImode),
+		      operand_subword (op1, 1, 1, DImode));
+      insns = get_insns ();
+      end_sequence ();
+
+      emit_no_conflict_block (insns, op0, op1, 0, op1);
+      DONE;
+    }
+
+  if (GET_CODE (op0) == MEM && ! reload_in_progress)
+    {
+      emit_insn (gen_storedi (operands[0], force_reg (DImode, operands[1])));
+      DONE;
+    }
+}")
+
+(define_insn ""
+ [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,Q")
+       (match_operand:DI 1 "reg_or_mem_operand" "r,Q,m,r"))]
+  "register_operand (operands[0], DImode)
+   || register_operand (operands[1], DImode)"
+  "*
+{
+  switch (which_alternative)
+    {
+    case 0:
+      if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
+	return \"cas %O0,%O1,r0\;cas %0,%1,r0\";
+      else
+	return \"cas %0,%1,r0\;cas %O0,%O1,r0\";
+    case 1:
+      /* Here we must see which word to load first.  We default to the
+	 low-order word unless it occurs in the address.  */
+      if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
+			     operands[1], 0))
+	return \"l%M1 %O0,%O1\;l%M1 %0,%1\";
+      else
+	return \"l%M1 %0,%1\;l%M1 %O0,%O1\";
+    case 2:
+      return \"get %O0,$%1\;ls %0,0(%O0)\;ls %O0,4(%O0)\";
+    case 3:
+      return \"st%M0 %1,%0\;st%M0 %O1,%O0\";
+    }
+}"
+  [(set_attr "type" "multi")
+   (set_attr "cc" "change0,change0,change0,none")
+   (set_attr "length" "4,12,8,8")])
+
+(define_insn "storedi"
+  [(set (match_operand:DI 0 "memory_operand" "=Q,m")
+	(match_operand:DI 1 "register_operand" "r,r"))
+   (clobber (match_scratch:SI 2 "=X,&b"))]
+  ""
+  "@
+   st%M0 %1,%0\;st%M0 %O1,%O0
+   get %2,$%0\;sts %1,0(%2)\;sts %O1,4(%2)"
+  [(set_attr "type" "multi,multi")
+   (set_attr "cc" "none,none")
+   (set_attr "length" "8,12")])
+
+(define_expand "reload_outdi"
+  [(set (match_operand:DI 0 "symbolic_memory_operand" "=m")
+	(match_operand:DI 1 "" "r"))
+   (match_operand:SI 2 "" "=&b")]
+  ""
+  "")
+
+;; Split symbolic memory operands differently.  We first load the address
+;; into a register and then do the two loads or stores.  We can only do
+;; this if operand_subword won't produce a SUBREG, which is only when
+;; operands[0] is a hard register.  Thus, these won't be used during the
+;; first insn scheduling pass.
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(match_operand:DI 1 "symbolic_memory_operand" ""))]
+  "GET_CODE (operands[0]) == REG
+   && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER"
+  [(set (match_dup 2) (match_dup 3))
+   (set (match_dup 4) (match_dup 5))
+   (set (match_dup 6) (match_dup 7))]
+  "
+{ operands[2] = operand_subword (operands[0], 1, 0, DImode);
+  operands[3] = XEXP (operands[1], 0);
+  operands[4] = operand_subword (operands[0], 0, 0, DImode);
+  operands[5] = gen_rtx (MEM, SImode, operands[2]);
+  operands[6] = operands[2];
+  operands[7] = gen_rtx (MEM, SImode,
+			 gen_rtx (PLUS, SImode, operands[2],
+				  gen_rtx (CONST_INT, VOIDmode, 4)));
+
+  if (operands[2] == 0 || operands[4] == 0)
+    FAIL;
+}")
+
+(define_split
+  [(set (match_operand:DI 0 "symbolic_memory_operand" "")
+	(match_operand:DI 1 "register_operand" ""))
+   (clobber (match_operand:SI 2 "register_operand" ""))] 
+  "GET_CODE (operands[0]) == REG
+   && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER"
+  [(set (match_dup 2) (match_dup 3))
+   (set (match_dup 4) (match_dup 5))
+   (set (match_dup 6) (match_dup 7))]
+  "
+{ operands[3] = XEXP (operands[0], 0);
+  operands[4] = gen_rtx (MEM, SImode, operands[2]);
+  operands[5] = operand_subword (operands[1], 0, 0, DImode);
+  operands[6] = gen_rtx (MEM, SImode,
+			 gen_rtx (PLUS, SImode, operands[2],
+				  gen_rtx (CONST_INT, VOIDmode, 4)));
+  operands[7] = operand_subword (operands[1], 1, 0, DImode);
+
+  if (operands[5] == 0 || operands[7] == 0)
+    FAIL;
+}")
+
+;; If the output is a register and the input is memory, we have to be careful
+;; and see which word needs to be loaded first.
+;;
+;; Note that this case doesn't have a CLOBBER.   Therefore, we must either
+;; be after reload or operand[0] must not be a MEM.  So we don't need a
+;; CLOBBER on the new insns either.
+;;
+;; Due to a bug in sched.c, we do not want to split this insn if both
+;; operands are registers and they overlap unless reload has completed.
+(define_split
+  [(set (match_operand:DI 0 "general_operand" "")
+	(match_operand:DI 1 "general_operand" ""))]
+  "! symbolic_memory_operand (operands[0], DImode)
+   && ! symbolic_memory_operand (operands[1], DImode)
+   && ! (GET_CODE (operands[0]) == REG
+         && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
+   && ! (GET_CODE (operands[1]) == REG
+         && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
+   && ! (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
+	 && ! reload_completed
+	 && reg_overlap_mentioned_p (operands[0], operands[1]))"
+  [(set (match_dup 2) (match_dup 3))
+   (set (match_dup 4) (match_dup 5))]
+  "
+{ if (GET_CODE (operands[0]) != REG
+      || ! refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
+			      operands[1], 0))
+    {
+      operands[2] = operand_subword (operands[0], 0, 0, DImode);
+      operands[3] = operand_subword (operands[1], 0, 0, DImode);
+      operands[4] = operand_subword (operands[0], 1, 0, DImode);
+      operands[5] = operand_subword (operands[1], 1, 0, DImode);
+    }
+  else
+    {
+      operands[2] = operand_subword (operands[0], 1, 0, DImode);
+      operands[3] = operand_subword (operands[1], 1, 0, DImode);
+      operands[4] = operand_subword (operands[0], 0, 0, DImode);
+      operands[5] = operand_subword (operands[1], 0, 0, DImode);
+    }
+
+  if (operands[2] == 0 || operands[3] == 0
+      || operands[4] == 0 || operands[5] == 0)
+    FAIL;
+}")
+
+(define_split
+ [(set (match_operand:DI 0 "general_operand" "")
+       (match_operand:DI 1 "general_operand" ""))
+  (clobber (match_operand:SI 6 "register_operand" ""))]
+  "! symbolic_memory_operand (operands[0], DImode)
+   && ! symbolic_memory_operand (operands[1], DImode)
+   && ! (GET_CODE (operands[0]) == REG
+         && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
+   && ! (GET_CODE (operands[1]) == REG
+         && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)"
+ [(parallel [(set (match_dup 2) (match_dup 3))
+	     (clobber (match_dup 7))])
+  (parallel [(set (match_dup 4) (match_dup 5))
+	     (clobber (match_dup 8))])]
+ "
+{ if (GET_CODE (operands[0]) != REG
+      || ! refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
+			      operands[1], 0))
+    {
+      operands[2] = operand_subword (operands[0], 0, 0, DImode);
+      operands[3] = operand_subword (operands[1], 0, 0, DImode);
+      operands[4] = operand_subword (operands[0], 1, 0, DImode);
+      operands[5] = operand_subword (operands[1], 1, 0, DImode);
+    }
+  else
+    {
+      operands[2] = operand_subword (operands[0], 1, 0, DImode);
+      operands[3] = operand_subword (operands[1], 1, 0, DImode);
+      operands[4] = operand_subword (operands[0], 0, 0, DImode);
+      operands[5] = operand_subword (operands[1], 0, 0, DImode);
+    }
+
+  if (operands[2] == 0 || operands[3] == 0
+      || operands[4] == 0 || operands[5] == 0)
+    FAIL;
+
+  /* We must be sure to make two different SCRATCH operands, since they
+     are not allowed to be shared.  After reload, however, we only have
+     a SCRATCH if we won't use the operand, so it is allowed to share it
+     then.  */
+  if (reload_completed || GET_CODE (operands[6]) != SCRATCH)
+    operands[7] = operands[8] = operands[6];
+  else
+    {
+      operands[7] = gen_rtx (SCRATCH, SImode);
+      operands[8] = gen_rtx (SCRATCH, SImode);
+    }
+}")
+
+;; Define move insns for SF, and DF.
+;;
+;; For register-register copies or a copy of something to itself, emit a
+;; single SET insn since it will likely be optimized away.
+;;
+;; Otherwise, emit a floating-point move operation unless both input and
+;; output are either constant, memory, or a non-floating-point hard register.
+(define_expand "movdf"
+  [(parallel [(set (match_operand:DF 0 "general_operand" "")
+		   (match_operand:DF 1 "general_operand" ""))
+	      (clobber (reg:SI 0))
+	      (clobber (reg:SI 15))])]
+  ""
+  "
+{ rtx op0 = operands[0];
+  rtx op1 = operands[1];
+
+  if (op0 == op1)
+    {
+      emit_insn (gen_rtx (SET, VOIDmode, op0, op1));
+      DONE;
+    }
+
+  if ((GET_CODE (op0) == MEM
+       || (GET_CODE (op0) == REG && REGNO (op0) < FIRST_PSEUDO_REGISTER
+	   && ! FP_REGNO_P (REGNO (op0))))
+      && (GET_CODE (op1) == MEM
+	  || GET_CODE (op1) == CONST_DOUBLE
+	  || (GET_CODE (op1) == REG && REGNO (op1) < FIRST_PSEUDO_REGISTER
+	      && ! FP_REGNO_P (REGNO (op1)) && ! rtx_equal_p (op0, op1))))
+    {
+      rtx insns;
+
+      if (GET_CODE (op1) == CONST_DOUBLE)
+	op1 = force_const_mem (DFmode, op1);
+
+      start_sequence ();
+      if (GET_CODE (operands[0]) != REG
+	  || ! refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
+				  operands[1]), 0)
+	{
+	  emit_move_insn (operand_subword (op0, 0, 1, DFmode),
+			  operand_subword_force (op1, 0, DFmode));
+	  emit_move_insn (operand_subword (op0, 1, 1, DFmode),
+			  operand_subword_force (op1, 1, DFmode));
+	}
+      else
+	{
+	  emit_move_insn (operand_subword (op0, 1, 1, DFmode),
+			  operand_subword_force (op1, 1, DFmode));
+	  emit_move_insn (operand_subword (op0, 0, 1, DFmode),
+			  operand_subword_force (op1, 0, DFmode));
+	}
+
+      insns = get_insns ();
+      end_sequence ();
+
+      emit_no_conflict_block (insns, op0, op1, 0, op1);
+      DONE;
+    }
+}")
+
+(define_expand "movsf"
+  [(parallel [(set (match_operand:SF 0 "general_operand" "")
+		   (match_operand:SF 1 "general_operand" ""))
+	      (clobber (reg:SI 0))
+	      (clobber (reg:SI 15))])]
+  ""
+  "
+{ rtx op0 = operands[0];
+  rtx op1 = operands[1];
+  
+  if (op0 == op1)
+    {
+      emit_insn (gen_rtx (SET, VOIDmode, op0, op1));
+      DONE;
+    }
+
+  if ((GET_CODE (op0) == MEM
+       || (GET_CODE (op0) == REG && REGNO (op0) < FIRST_PSEUDO_REGISTER
+	   && ! FP_REGNO_P (REGNO (op0))))
+       && (GET_CODE (op1) == MEM
+	   || GET_CODE (op1) == CONST_DOUBLE
+	   || (GET_CODE (op1) == REG && REGNO (op1) < FIRST_PSEUDO_REGISTER
+	       && ! FP_REGNO_P (REGNO (op1)))))
+    {
+      rtx last;
+
+      if (GET_CODE (op1) == CONST_DOUBLE)
+	op1 = force_const_mem (SFmode, op1);
+
+      last = emit_move_insn (operand_subword (op0, 0, 1, SFmode),
+			     operand_subword_force (op1, 0, SFmode));
+
+      REG_NOTES (last) = gen_rtx (EXPR_LIST, REG_EQUAL, op1, REG_NOTES (last));
+      DONE;
+    }
+}")
+
+;; Define the move insns for SF and DF.  Check for all general regs
+;; in the FP insns and make them non-FP if so.  Do the same if the input and
+;; output are the same (the insn will be deleted in this case and we don't
+;; want to think there are FP insns when there might not be).
+(define_insn ""
+  [(set (match_operand:SF 0 "general_operand" "=*frg")
+	(match_dup 0))]
+  ""
+  "nopr r0"
+  [(set_attr "type" "address")
+   (set_attr "length" "2")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "general_operand" "=r,*fr,r,r,Q,m,frg")
+	(match_operand:SF 1 "general_operand" "r,0,Q,m,r,r,frg"))
+   (clobber (match_operand:SI 2 "reg_0_operand" "=&z,z,z,z,z,z,z"))
+   (clobber (match_operand:SI 3 "reg_15_operand" "=&t,t,t,t,t,t,t"))]
+  ""
+  "*
+{ switch (which_alternative)
+    {
+    case 0:
+      return \"cas %0,%1,r0\";
+    case 1:
+      return \"nopr r0\";
+    case 2:
+      return \"l%M1 %0,%1\";
+    case 3:
+      return \"load %0,%1\";
+    case 4:
+      return \"st%M0 %1,%0\";
+    case 5:
+      return \"store %1,%0,%3\";
+    default:
+      return output_fpop (SET, operands[0], operands[1], 0, insn);
+    }
+}"
+  [(set_attr "type" "address,address,load,load,store,store,fp")
+   (set_attr "length" "2,2,*,*,*,*,*")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "general_operand" "=*frg")
+	(match_dup 0))]
+  ""
+  "nopr r0"
+  [(set_attr "type" "address")
+   (set_attr "length" "2")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "general_operand" "=r,*fr,r,r,Q,m,frg")
+	(match_operand:DF 1 "general_operand" "r,0,Q,m,r,r,*frg"))
+   (clobber (match_operand:SI 2 "reg_0_operand" "=&z,z,z,z,z,z,z"))
+   (clobber (match_operand:SI 3 "reg_15_operand" "=&t,t,t,t,t,t,t"))]
+  ""
+  "*
+{ switch (which_alternative)
+    {
+    case 0:
+      if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
+	return \"cas %O0,%O1,r0\;cas %0,%1,r0\";
+      else
+	return \"cas %0,%1,r0\;cas %O0,%O1,r0\";
+    case 1:
+      return \"nopr r0\";
+    case 2:
+      /* Here we must see which word to load first.  We default to the
+	 low-order word unless it occurs in the address.  */
+      if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
+			     operands[1], 0))
+	return \"l%M1 %O0,%O1\;l%M1 %0,%1\";
+      else
+	return \"l%M1 %0,%1\;l%M1 %O0,%O1\";
+    case 3:
+      return \"get %3,$%1\;ls %0,0(%3)\;ls %O0,4(%3)\";
+    case 4:
+      return \"st%M0 %1,%0\;st%M0 %O1,%O0\";
+    case 5:
+      return \"get %3,$%0\;sts %1,0(%3)\;sts %O1,4(%3)\";
+    default:
+      return output_fpop (SET, operands[0], operands[1], 0, insn);
+    }
+}"
+  [(set_attr "type" "address,multi,multi,multi,multi,multi,fp")
+   (set_attr "length" "2,4,*,*,*,*,*")])
+
+;; Split all the above cases that involve multiple insns and no floating-point
+;; data block.  If before reload, we can make a SCRATCH.  Otherwise, use
+;; register 15.
+
+(define_split
+  [(set (match_operand:DF 0 "register_operand" "")
+	(match_operand:DF 1 "symbolic_memory_operand" ""))
+   (clobber (reg:SI 0))
+   (clobber (reg:SI 15))]
+  "GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 16"
+  [(set (reg:SI 15) (match_dup 2))
+   (set (match_dup 3) (match_dup 4))
+   (set (match_dup 5) (match_dup 6))]
+  "
+{ operands[2] = XEXP (operands[1], 0);
+  operands[3] = operand_subword (operands[0], 0, 0, DFmode);
+  operands[4] = gen_rtx (MEM, SImode, gen_rtx (REG, SImode, 15));
+  operands[5] = operand_subword (operands[0], 0, 1, DFmode);
+  operands[6] = gen_rtx (MEM, SImode,
+			 gen_rtx (PLUS, SImode, gen_rtx (REG, SImode, 15),
+				  gen_rtx (CONST_INT, VOIDmode, 4)));
+
+  if (operands[3] == 0 || operands[5] == 0)
+    FAIL;
+}")
+
+(define_split
+  [(set (match_operand:DF 0 "symbolic_memory_operand" "")
+	(match_operand:DF 1 "register_operand" ""))
+   (clobber (reg:SI 0))
+   (clobber (reg:SI 15))]
+  "GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 16"
+  [(set (reg:SI 15) (match_dup 2))
+   (set (match_dup 3) (match_dup 4))
+   (set (match_dup 5) (match_dup 6))]
+  "
+{ operands[2] = XEXP (operands[0], 0);
+  operands[3] = gen_rtx (MEM, SImode, gen_rtx (REG, SImode, 15));
+  operands[4] = operand_subword (operands[1], 0, 0, DFmode);
+  operands[5] = gen_rtx (MEM, SImode,
+			 gen_rtx (PLUS, SImode, gen_rtx (REG, SImode, 15),
+				  gen_rtx (CONST_INT, VOIDmode, 4)));
+  operands[6] = operand_subword (operands[1], 1, 0, DFmode);
+
+  if (operands[4] == 0 || operands[6] == 0)
+    FAIL;
+}")
+
+;; If the output is a register and the input is memory, we have to be careful
+;; and see which word needs to be loaded first.  We also cannot to the
+;; split if the input is a constant because it would result in invalid
+;; insns.  When the output is a MEM, we must put a CLOBBER on each of the
+;; resulting insn, when it is not a MEM, we must not.
+(define_split
+  [(set (match_operand:DF 0 "memory_operand" "")
+	(match_operand:DF 1 "register_operand" ""))
+   (clobber (reg:SI 0))
+   (clobber (reg:SI 15))]
+  "GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 15"
+  [(parallel [(set (match_dup 2) (match_dup 3))
+	      (clobber (match_dup 6))])
+   (parallel [(set (match_dup 4) (match_dup 5))
+	      (clobber (match_dup 7))])]
+  "
+{ operands[2] = operand_subword (operands[0], 0, 0, DFmode);
+  operands[3] = operand_subword (operands[1], 0, 0, DFmode);
+  operands[4] = operand_subword (operands[0], 1, 0, DFmode);
+  operands[5] = operand_subword (operands[1], 1, 0, DFmode);
+
+  if (operands[2] == 0 || operands[3] == 0
+      || operands[4] == 0 || operands[5] == 0)
+    FAIL;
+
+  if (reload_completed)
+    operands[6] = operands[7] = gen_rtx (REG, SImode, 15);
+  else
+    {
+      operands[6] = gen_rtx (SCRATCH, SImode);
+      operands[7] = gen_rtx (SCRATCH, SImode);
+    }
+}")
+
+(define_split
+  [(set (match_operand:DF 0 "nonmemory_operand" "")
+	(match_operand:DF 1 "general_operand" ""))
+   (clobber (reg:SI 0))
+   (clobber (reg:SI 15))]
+  "! symbolic_memory_operand (operands[1], DFmode)
+   && GET_CODE (operands[1]) != CONST_DOUBLE
+   && (GET_CODE (operands[0]) != REG || REGNO (operands[0]) < 15)
+   && (GET_CODE (operands[1]) != REG || REGNO (operands[1]) < 15)
+   && (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == REG)"
+  [(set (match_dup 2) (match_dup 3))
+   (set (match_dup 4) (match_dup 5))]
+  "
+{ if (GET_CODE (operands[0]) != REG
+      || ! refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
+			      operands[1], 0))
+    {
+      operands[2] = operand_subword (operands[0], 0, 0, DFmode);
+      operands[3] = operand_subword (operands[1], 0, 0, DFmode);
+      operands[4] = operand_subword (operands[0], 1, 0, DFmode);
+      operands[5] = operand_subword (operands[1], 1, 0, DFmode);
+    }
+  else
+    {
+      operands[2] = operand_subword (operands[0], 1, 0, DFmode);
+      operands[3] = operand_subword (operands[1], 1, 0, DFmode);
+      operands[4] = operand_subword (operands[0], 0, 0, DFmode);
+      operands[5] = operand_subword (operands[1], 0, 0, DFmode);
+    }
+
+  if (operands[2] == 0 || operands[3] == 0
+      || operands[4] == 0 || operands[5] == 0)
+    FAIL;
+}")
+
+;; Conversions from one integer mode to another.
+;; It is possible sometimes to sign- or zero-extend while fetching from memory.
+;;
+;; First, sign-extensions:
+(define_expand "extendhisi2"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
+  ""
+  "")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=b")
+	(sign_extend:SI (match_operand:HI 1 "symbolic_memory_operand" "m")))]
+  ""
+  "loadha %0,%1"
+  [(set_attr "type" "load")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r,r,b")
+	(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,Q,m")))]
+  ""
+  "@
+   exts %0,%1
+   lha%M1 %0,%1
+   loadha %0,%1"
+  [(set_attr "type" "arith,load,load")
+   (set_attr "length" "2,*,*")])
+
+(define_expand "extendqisi2"
+  [(set (match_dup 2)
+	(ashift:SI (match_operand:QI 1 "register_operand" "")
+		   (const_int 24)))
+   (set (match_operand:SI 0 "register_operand" "")
+	(ashiftrt:SI (match_dup 2)
+		     (const_int 24)))]
+  ""
+  "
+{ operands[1] = gen_lowpart (SImode, operands[1]);
+  operands[2] = gen_reg_rtx (SImode); }")
+
+(define_expand "extendqihi2"
+  [(set (match_dup 2)
+	(ashift:SI (match_operand:QI 1 "register_operand" "")
+		   (const_int 24)))
+   (set (match_operand:HI 0 "register_operand" "")
+	(ashiftrt:SI (match_dup 2)
+		     (const_int 24)))]
+  ""
+  "
+{ operands[0] = gen_lowpart (SImode, operands[0]);
+  operands[1] = gen_lowpart (SImode, operands[1]);
+  operands[2] = gen_reg_rtx (SImode); }")
+
+;; Define peepholes to eliminate an instruction when we are doing a sign
+;; extension but cannot clobber the input.
+;;
+;; In this case we will shift left 24 bits, but need a copy first.  The shift
+;; can be replaced by a "mc03" instruction, but this can only be done if
+;; followed by the right shift of 24 or more bits.
+(define_peephole
+  [(set (match_operand:SI 0 "register_operand" "")
+	(subreg:SI (match_operand:QI 1 "register_operand" "") 0))
+   (set (match_dup 0)
+	(ashift:SI (match_dup 0)
+		   (const_int 24)))
+   (set (match_dup 0)
+	(ashiftrt:SI (match_dup 0)
+		     (match_operand:SI 2 "const_int_operand" "")))]
+  "INTVAL (operands[2]) >= 24"
+  "mc03 %0,%1\;sari16 %0,%S2"
+ [(set_attr "type" "multi")
+  (set_attr "length" "4")
+  (set_attr "cc" "sets")])
+
+;; Now zero extensions:
+(define_expand "zero_extendhisi2"
+  [(set (match_operand:SI 0 "register_operand" "b")
+	(zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
+  ""
+  "")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=b")
+	(zero_extend:SI (match_operand:HI 1 "symbolic_memory_operand" "m")))]
+  ""
+  "loadh %0,%1"
+  [(set_attr "type" "load")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r,r,b")
+	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,Q,m")))]
+  ""
+  "@
+   nilz %0,%1,65535
+   lh%N1 %0,%1
+   loadh %0,%1"
+  [(set_attr "type" "arith,loadz,load")])
+
+(define_expand "zero_extendqisi2"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
+  ""
+  "")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=b")
+	(zero_extend:SI (match_operand:QI 1 "symbolic_memory_operand" "m")))]
+  ""
+  "loadc %0,%1"
+  [(set_attr "type" "load")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r,r,b")
+	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,Q,m")))]
+  ""
+  "@
+   nilz %0,%1,255
+   lc%M1 %0,%1
+   loadc %0,%1"
+  [(set_attr "type" "arith,load,load")])
+
+(define_expand "zero_extendqihi2"
+  [(set (match_operand:HI 0 "register_operand" "")
+	(zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
+  ""
+  "")
+
+(define_insn ""
+  [(set (match_operand:HI 0 "register_operand" "=b")
+	(zero_extend:HI (match_operand:QI 1 "symbolic_memory_operand" "m")))]
+  ""
+  "loadc %0,%1"
+  [(set_attr "type" "load")])
+
+(define_insn ""
+  [(set (match_operand:HI 0 "register_operand" "=r,r,b")
+	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,Q,m")))]
+  ""
+  "@
+   nilz %0,%1,255
+   lc%M1 %0,%1
+   loadc %0,%1"
+  [(set_attr "type" "arith,load,load")])
+
+;; Various extract and insertion operations.
+(define_expand "extzv"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(zero_extract:SI (match_operand:SI 1 "register_operand" "")
+			 (match_operand:SI 2 "const_int_operand" "")
+			 (match_operand:SI 3 "const_int_operand" "")))]
+  ""
+  "
+{
+  if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 8)
+    FAIL;
+
+  if (GET_CODE (operands[3]) != CONST_INT)
+    FAIL;
+
+  if (INTVAL (operands[3]) != 0 && INTVAL (operands[3]) != 8
+      && INTVAL (operands[3]) != 16 && INTVAL (operands[3]) != 24)
+    FAIL;
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=&r")
+	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
+			 (const_int 8)
+			 (match_operand:SI 2 "const_int_operand" "n")))]
+  "(INTVAL (operands[2]) & 7) == 0"
+  "lis %0,0\;mc3%B2 %0,%1"
+  [(set_attr "type" "multi")
+   (set_attr "cc" "change0")])
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "=&r")
+	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
+			 (const_int 8)
+			 (match_operand:SI 2 "const_int_operand" "n")))]
+  "(INTVAL (operands[2]) & 7) == 0"
+  [(set (match_dup 0) (const_int 0))
+   (set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 24))
+	(zero_extract:SI (match_dup 1) (const_int 8) (match_dup 2)))]
+  "")
+
+(define_insn ""
+  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
+			 (const_int 8)
+			 (const_int 24))
+	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
+			 (const_int 8)
+			 (match_operand:SI 2 "const_int_operand" "n")))]
+  "(INTVAL (operands[2]) & 7) == 0"
+  "mc3%B2 %0,%1"
+  [(set_attr "type" "address")
+   (set_attr "length" "2")])
+
+(define_expand "insv"
+  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "")
+			 (match_operand:SI 1 "const_int_operand" "")
+			 (match_operand:SI 2 "const_int_operand" ""))
+	(match_operand:SI 3 "register_operand" ""))]
+  ""
+  "
+{
+  if (GET_CODE (operands[2]) != CONST_INT)
+    FAIL;
+
+  if (GET_CODE (operands[1]) != CONST_INT)
+    FAIL;
+
+  if (INTVAL (operands[1]) == 1)
+    {
+      emit_insn (gen_bit_insv (operands[0], operands[1], operands[2],
+			       operands[3]));
+      DONE;
+    }
+  else if (INTVAL (operands[1]) == 8
+	   && (INTVAL (operands[2]) % 8 == 0))
+    ;				/* Accept aligned byte-wide field. */
+  else
+    FAIL;
+}")
+
+;; For a single-bit insert, it is better to explicitly generate references
+;; to the T bit.  We will call the T bit "CC0" because it can be clobbered
+;; by some CC0 sets (single-bit tests).
+
+(define_expand "bit_insv"
+  [(set (cc0)
+	(zero_extract:SI (match_operand:SI 3 "register_operand" "")
+			 (const_int 1)
+			 (const_int 31)))
+  (set (zero_extract:SI (match_operand:SI 0 "register_operand" "")
+			(match_operand:SI 1 "const_int_operand" "")
+			(match_operand:SI 2 "const_int_operand" ""))
+       (ne (cc0) (const_int 0)))]
+  ""
+  "")
+	
+(define_insn ""
+  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
+			 (const_int 8)
+			 (match_operand:SI 1 "const_int_operand" "n"))
+	(match_operand:SI 2 "register_operand" "r"))]
+  "(INTVAL (operands[1]) & 7) == 0"
+  "mc%B1%.3 %0,%2"
+  [(set_attr "type" "address")
+   (set_attr "length" "2")])
+
+;; This pattern cannot have any input reloads since if references CC0.
+;; So we have to add code to support memory, which is the only other
+;; thing that a "register_operand" can become.  There is still a problem
+;; if the address isn't valid and *it* needs a reload, but there is no
+;; way to solve that problem, so let's hope it never happens.
+
+(define_insn ""
+  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,m")
+			 (const_int 1)
+			 (match_operand:SI 1 "const_int_operand" "n,m"))
+	(ne (cc0) (const_int 0)))
+   (match_scratch 2 "=X,b")]
+  ""
+  "@
+   mftbi%t1 %0,%S1
+   l%M0 %2,%0\;mftb%t1 %2,%S1\;st%M0 %2,%0"
+  [(set_attr "type" "*,multi")
+   (set_attr "cc" "none,none")
+   (set_attr "length" "2,10")])
+
+;; Arithmetic instructions.  First, add and subtract.
+;;
+;; It may be that the second input is either large or small enough that
+;; the operation cannot be done in a single insn.  In that case, emit two.
+(define_expand "addsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(plus:SI (match_operand:SI 1 "register_operand" "")
+		 (match_operand:SI 2 "nonmemory_operand" "")))]
+  ""
+  "
+{
+  if (GET_CODE (operands[2]) == CONST_INT
+      && (unsigned) (INTVAL (operands[2]) + 0x8000) >= 0x10000
+      && (INTVAL (operands[2]) & 0xffff) != 0)
+    {
+      int low = INTVAL (operands[2]) & 0xffff;
+      int high = (unsigned) INTVAL (operands[2]) >> 16;
+
+      if (low & 0x8000)
+	high++, low |= 0xffff0000;
+
+      emit_insn (gen_addsi3 (operands[0], operands[1],
+			     gen_rtx (CONST_INT, VOIDmode, high << 16)));
+      operands[1] = operands[0];
+      operands[2] = gen_rtx (CONST_INT, VOIDmode, low);
+    }
+}")
+
+;; Put the insn to add a symbolic constant to a register separately to
+;; improve register allocation since it has different register requirements.
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=b")
+	(plus:SI (match_operand:SI 1 "register_operand" "%b")
+		 (match_operand:SI 2 "romp_symbolic_operand" "s")))]
+   ""
+   "get %0,$%2(%1)"
+   [(set_attr "type" "address")
+    (set_attr "length" "8")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,b")
+	(plus:SI (match_operand:SI 1 "reg_or_add_operand" "%0,0,r,b,0,r,b")
+		 (match_operand:SI 2 "reg_or_add_operand" "I,J,K,M,r,b,s")))]
+  "register_operand (operands[1], SImode)
+   || register_operand (operands[2], SImode)"
+  "@
+   ais %0,%2
+   sis %0,%n2
+   ail %0,%1,%2
+   cau %0,%H2(%1)
+   a %0,%2
+   cas %0,%1,%2
+   get %0,$%2(%1)"
+  [(set_attr "type" "arith,arith,arith,address,arith,address,misc")
+   (set_attr "length" "2,2,4,4,2,2,8")])
+
+;; Now subtract.
+;;
+;; 1.	If third operand is constant integer, convert it to add of the negative
+;;	of that integer.
+;; 2.	If the second operand is not a valid constant integer, force it into a
+;;	register.
+(define_expand "subsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(minus:SI (match_operand:SI 1 "reg_or_any_cint_operand" "")
+		  (match_operand:SI 2 "reg_or_any_cint_operand" "")))]
+  ""
+  "
+{
+  if (GET_CODE (operands [2]) == CONST_INT)
+    {
+      emit_insn (gen_addsi3 (operands[0], operands[1], 
+			     gen_rtx (CONST_INT,
+				      VOIDmode, - INTVAL (operands[2]))));
+      DONE;
+    }
+  else
+    operands[2] = force_reg (SImode, operands[2]);
+
+  if (GET_CODE (operands[1]) != CONST_INT
+      || (unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000)
+    operands[1] = force_reg (SImode, operands[1]);
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
+	(minus:SI (match_operand:SI 1 "reg_or_D_operand" "K,0,r")
+		  (match_operand:SI 2 "register_operand" "r,r,0")))]
+  ""
+  "@
+   sfi %0,%2,%1
+   s %0,%2
+   sf %0,%1"
+  [(set_attr "length" "4,2,2")])
+
+;; Multiply either calls a special RT routine or is done in-line, depending
+;; on the value of a -m flag.
+;;
+;; First define the way we call the subroutine.
+(define_expand "mulsi3_subr"
+  [(set (reg:SI 2) (match_operand:SI 1 "register_operand" ""))
+   (set (reg:SI 3) (match_operand:SI 2 "register_operand" ""))
+   (parallel [(set (reg:SI 2) (mult:SI (reg:SI 2) (reg:SI 3)))
+	      (clobber (reg:SI 0))
+	      (clobber (reg:SI 15))])
+   (set (match_operand:SI 0 "register_operand" "")
+	(reg:SI 2))]
+  ""
+  "")
+
+(define_expand "mulsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(mult:SI (match_operand:SI 1 "register_operand" "")
+		 (match_operand:SI 2 "register_operand" "")))]
+  ""
+  "
+{
+  if (! TARGET_IN_LINE_MUL)
+    {
+      emit_insn (gen_mulsi3_subr (operands[0], operands[1], operands[2]));
+      DONE;
+    }
+}")
+
+;; Define the patterns to match.
+;; We would like to provide a delay slot for the insns that call internal
+;; routines, but doing so is risky since reorg will think that the use of
+;; r2 and r3 is completed in the insn needing the delay slot.  Also, it
+;; won't know that the cc will be clobbered.  So take the safe approach
+;; and don't give them delay slots.
+(define_insn ""
+  [(set (reg:SI 2)
+	(mult:SI (reg:SI 2) (reg:SI 3)))
+   (clobber (reg:SI 0))
+   (clobber (reg:SI 15))]
+  "! TARGET_IN_LINE_MUL"
+  "bali%# r15,lmul$$"
+  [(set_attr "type" "misc")
+   (set_attr "in_delay_slot" "no")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=&r")
+	(mult:SI (match_operand:SI 1 "register_operand" "%r")
+		 (match_operand:SI 2 "register_operand" "r")))]
+  "TARGET_IN_LINE_MUL"
+  "*
+{ return output_in_line_mul (); }"
+  [(set_attr "length" "38")
+   (set_attr "type" "multi")])
+
+;; Handle divide and modulus.  The same function returns both values,
+;; so use divmodsi4.  This divides arg 1 by arg 2 with quotient to go
+;; into arg 0 and remainder in arg 3.
+;;
+;; We want to put REG_EQUAL notes for the two outputs.  So we need a
+;; function to do everything else.
+(define_expand "divmodsi4_doit"
+  [(set (reg:SI 2)
+	(match_operand:SI 0 "register_operand" ""))
+   (set (reg:SI 3)
+	(match_operand:SI 1 "register_operand" ""))
+   (parallel [(set (reg:SI 2) (div:SI (reg:SI 2) (reg:SI 3)))
+	      (set (reg:SI 3) (mod:SI (reg:SI 2) (reg:SI 3)))
+	      (clobber (reg:SI 0))
+	      (clobber (reg:SI 15))])]
+  ""
+  "")
+
+(define_expand "divmodsi4"
+  [(parallel [(set (match_operand:SI 0 "register_operand" "")
+		   (div:SI (match_operand:SI 1 "register_operand" "")
+			   (match_operand:SI 2 "register_operand" "")))
+	      (set (match_operand:SI 3 "register_operand" "")
+		   (mod:SI (match_dup 1) (match_dup 2)))])]
+  ""
+  "
+{
+  rtx insn;
+
+  emit_insn (gen_divmodsi4_doit (operands[1], operands[2]));
+  insn = emit_move_insn (operands[0], gen_rtx (REG, SImode, 2));
+  REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL,
+			      gen_rtx (DIV, SImode, operands[1],
+				       operands[2]),
+			      REG_NOTES (insn));
+  insn = emit_move_insn (operands[3], gen_rtx (REG, SImode, 3));
+  REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL,
+			      gen_rtx (MOD, SImode, operands[1],
+				       operands[2]),
+			      REG_NOTES (insn));
+  DONE;
+}")
+
+(define_insn ""
+  [(set (reg:SI 2)
+	(div:SI (reg:SI 2) (reg:SI 3)))
+   (set (reg:SI 3)
+	(mod:SI (reg:SI 2) (reg:SI 3)))
+   (clobber (reg:SI 0))
+   (clobber (reg:SI 15))]
+  ""
+  "bali%# r15,ldiv$$"
+  [(set_attr "type" "misc")
+   (set_attr "in_delay_slot" "no")])
+
+;; Similarly for unsigned divide.
+(define_expand "udivmodsi4_doit"
+  [(set (reg:SI 2)
+	(match_operand:SI 0 "register_operand" ""))
+   (set (reg:SI 3)
+	(match_operand:SI 1 "register_operand" ""))
+   (parallel [(set (reg:SI 2) (udiv:SI (reg:SI 2) (reg:SI 3)))
+	      (set (reg:SI 3) (umod:SI (reg:SI 2) (reg:SI 3)))
+	      (clobber (reg:SI 0))
+	      (clobber (reg:SI 15))])]
+  ""
+  "")
+
+(define_expand "udivmodsi4"
+  [(parallel [(set (match_operand:SI 0 "register_operand" "")
+		   (udiv:SI (match_operand:SI 1 "register_operand" "")
+			    (match_operand:SI 2 "register_operand" "")))
+	      (set (match_operand:SI 3 "register_operand" "")
+		   (umod:SI (match_dup 1) (match_dup 2)))])]
+  ""
+  "
+{
+  rtx insn;
+
+  emit_insn (gen_udivmodsi4_doit (operands[1], operands[2]));
+  insn = emit_move_insn (operands[0], gen_rtx (REG, SImode, 2));
+  REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL,
+			      gen_rtx (UDIV, SImode, operands[1],
+				       operands[2]),
+			      REG_NOTES (insn));
+  insn = emit_move_insn (operands[3], gen_rtx (REG, SImode, 3));
+  REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL,
+			      gen_rtx (UMOD, SImode, operands[1],
+				       operands[2]),
+			      REG_NOTES (insn));
+  DONE;
+}")
+
+(define_insn ""
+  [(set (reg:SI 2)
+	(udiv:SI (reg:SI 2) (reg:SI 3)))
+   (set (reg:SI 3)
+	(umod:SI (reg:SI 2) (reg:SI 3)))
+   (clobber (reg:SI 0))
+   (clobber (reg:SI 15))]
+  ""
+  "bali%# r15,uldiv$$"
+  [(set_attr "type" "misc")
+   (set_attr "in_delay_slot" "no")])
+
+;; Define DImode arithmetic operations.
+;;
+;; It is possible to do certain adds and subtracts with constants in a single
+;; insn, but it doesn't seem worth the trouble.
+;;
+;; Don't use DEFINE_SPLIT on these because the dependency on CC can't be
+;; easily tracked in that case!
+(define_insn "adddi3"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(plus:DI (match_operand:DI 1 "register_operand" "%0")
+		 (match_operand:DI 2 "register_operand" "r")))]
+  ""
+  "a %O0,%O2\;ae %0,%2"
+  [(set_attr "type" "multi")])
+
+(define_insn "subdi3"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(minus:DI (match_operand:DI 1 "register_operand" "0")
+		  (match_operand:DI 2 "register_operand" "r")))]
+  ""
+  "s %O0,%O2\;se %0,%2"
+  [(set_attr "type" "multi")])
+
+(define_insn "negdi2"
+  [(set (match_operand:DI 0 "register_operand" "=r,&r")
+	(neg:DI (match_operand:DI 1 "register_operand" "0,r")))]
+  ""
+  "twoc %O0,%O1\;onec %0,%1\;aei %0,%0,0"
+  [(set_attr "type" "multi")
+   (set_attr "length" "8")])
+
+;; Unary arithmetic operations.
+(define_insn "abssi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(abs:SI (match_operand:SI 1 "register_operand" "r")))]
+  ""
+  "abs %0,%1"
+  [(set_attr "length" "2")])
+
+(define_insn "negsi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(neg:SI (match_operand:SI 1 "register_operand" "r")))]
+  ""
+  "twoc %0,%1"
+  [(set_attr "length" "2")])
+
+(define_insn "one_cmplsi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(not:SI (match_operand:SI 1 "register_operand" "r")))]
+  ""
+  "onec %0,%1"
+  [(set_attr "length" "2")])
+
+
+;; Logical insns: AND, IOR, and XOR
+;;
+;; If the operation is being performed on a 32-bit constant such that
+;; it cannot be done in one insn, do it in two.  We may lose a bit on
+;; CSE in pathological cases, but it seems better doing it this way.
+(define_expand "andsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(and:SI (match_operand:SI 1 "register_operand" "")
+		(match_operand:SI 2 "reg_or_any_cint_operand" "")))]
+  ""
+  "
+{
+  if (GET_CODE (operands[2]) == CONST_INT)
+    {
+      int top = (unsigned) INTVAL (operands[2]) >> 16;
+      int bottom = INTVAL (operands[2]) & 0xffff;
+
+      if (top != 0 && top != 0xffff && bottom != 0 && bottom != 0xffff)
+	{
+	  emit_insn (gen_andsi3 (operands[0], operands[1],
+				 gen_rtx (CONST_INT, VOIDmode,
+					  (top << 16) | 0xffff)));
+	  operands[1] = operands[0];
+	  operands[2] = gen_rtx (CONST_INT, VOIDmode, 0xffff0000 | bottom);
+	}
+    }
+}");
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
+	(and:SI (match_operand:SI 1 "reg_or_and_operand" "%0,r,0")
+		(match_operand:SI 2 "reg_or_and_operand" "P,LMO,r")))]
+  "register_operand (operands[1], SImode)
+   || register_operand (operands[2], SImode)"
+  "@
+   clrb%k2 %0,%b2
+   ni%z2 %0,%1,%Z2
+   n %0,%2"
+  [(set_attr "length" "2,4,2")])
+
+;; logical OR (IOR)
+(define_expand "iorsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(ior:SI (match_operand:SI 1 "register_operand" "")
+		(match_operand:SI 2 "reg_or_any_cint_operand" "")))]
+  ""
+  "
+{
+  if (GET_CODE (operands[2]) == CONST_INT)
+    {
+      int top = (unsigned) INTVAL (operands[2]) >> 16;
+      int bottom = INTVAL (operands[2]) & 0xffff;
+
+      if (top != 0 && bottom != 0)
+	{
+	  emit_insn (gen_iorsi3 (operands[0], operands[1],
+				 gen_rtx (CONST_INT, VOIDmode, (top << 16))));
+	  operands[1] = operands[0];
+	  operands[2] = gen_rtx (CONST_INT, VOIDmode, bottom);
+	}
+    }
+}");
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
+	(ior:SI (match_operand:SI 1 "reg_or_cint_operand" "%0,r,0")
+		(match_operand:SI 2 "reg_or_cint_operand" "N,LM,r")))]
+  "register_operand (operands[1], SImode)
+   || register_operand (operands[2], SImode)"
+  "@
+   setb%h2 %0,%b2
+   oi%h2 %0,%1,%H2
+   o %0,%2"
+  [(set_attr "length" "2,4,2")])
+
+;; exclusive-or (XOR)
+(define_expand "xorsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(xor:SI (match_operand:SI 1 "register_operand" "")
+		(match_operand:SI 2 "reg_or_any_cint_operand" "")))]
+  ""
+  "
+{
+  if (GET_CODE (operands[2]) == CONST_INT)
+    {
+      int top = (unsigned) INTVAL (operands[2]) >> 16;
+      int bottom = INTVAL (operands[2]) & 0xffff;
+
+      if (top == 0xffff && bottom == 0xffff)
+	{
+	  emit_insn (gen_one_cmplsi2 (operands[0], operands[1]));
+	  DONE;
+	}
+      else if (top != 0 && bottom != 0)
+	{
+	  emit_insn (gen_xorsi3 (operands[0], operands[1],
+				 gen_rtx (CONST_INT, VOIDmode, (top << 16))));
+	  operands[1] = operands[0];
+	  operands[2] = gen_rtx (CONST_INT, VOIDmode, bottom);
+	}
+    }
+}");
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
+	(xor:SI (match_operand:SI 1 "reg_or_cint_operand" "%r,0")
+		(match_operand:SI 2 "reg_or_cint_operand" "LM,r")))]
+  "register_operand (operands[1], SImode)
+   || register_operand (operands[2], SImode)"
+  "@
+   xi%h2 %0,%1,%H2
+   x %0,%2"
+  [(set_attr "length" "4,2")])
+
+;; Various shift insns
+(define_insn "ashrsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
+	(ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
+		     (match_operand:QI 2 "reg_or_cint_operand" "r,n")))]
+  ""
+  "@
+   sar %0,%2
+   sari%s2 %0,%S2"
+  [(set_attr "length" "2")])
+
+(define_insn "lshrsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
+	(lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
+		     (match_operand:QI 2 "reg_or_cint_operand" "r,n")))]
+  ""
+  "@
+   sr %0,%2
+   sri%s2 %0,%S2"
+  [(set_attr "length" "2")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(ashift:SI (match_operand:SI 1 "register_operand" "b")
+		   (const_int 1)))]
+  ""
+  "cas %0,%1,%1"
+  [(set_attr "length" "2")
+   (set_attr "type" "address")])
+
+(define_insn "ashlsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
+	(ashift:SI (match_operand:SI 1 "register_operand" "0,0")
+		   (match_operand:QI 2 "reg_or_cint_operand" "r,n")))]
+  ""
+  "@
+   sl %0,%2
+   sli%s2 %0,%S2"
+  [(set_attr "length" "2")])
+
+;; Function call insns:
+;;
+;; On the ROMP, &fcn is actually a pointer to the data area, which is passed
+;; to the function in r0.  &.fcn is the actual starting address of the
+;; function.  Also, the word at &fcn contains &.fcn.
+;;
+;; For both functions that do and don't return values, there are two cases:
+;; where the function's address is a constant, and where it isn't.
+;;
+;; Operand 1 (2 for `call_value') is the number of arguments and is not used.
+(define_expand "call"
+  [(use (reg:SI 0))
+   (parallel [(call (mem:SI (match_operand:SI 0 "address_operand" ""))
+		    (match_operand 1 "" ""))
+	      (clobber (reg:SI 15))])]
+  ""
+  "
+{
+  if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
+    abort();
+
+  operands[0] = XEXP (operands[0], 0);
+  if (GET_CODE (operands[0]) == SYMBOL_REF)
+    {
+      extern rtx get_symref ();
+      char *real_fcnname =
+		(char *) alloca (strlen (XSTR (operands[0], 0)) + 2);
+
+      /* Copy the data area address to r0.  */
+      emit_move_insn (gen_rtx (REG, SImode, 0),
+		      force_reg (SImode, operands[0]));
+      strcpy (real_fcnname, \".\");
+      strcat (real_fcnname, XSTR (operands[0], 0));
+      operands[0] = get_symref (real_fcnname);
+    }
+  else
+    {
+      rtx data_access;
+
+      emit_move_insn (gen_rtx (REG, SImode, 0),
+		      force_reg (SImode, operands[0]));
+      data_access = gen_rtx (MEM, SImode, operands[0]);
+      RTX_UNCHANGING_P (data_access) = 1;
+      operands[0] = copy_to_reg (data_access);
+    }
+}")
+
+(define_insn ""
+  [(call (mem:SI (match_operand:SI 0 "register_operand" "b"))
+	 (match_operand 1 "" "g"))
+   (clobber (reg:SI 15))]
+  ""
+  "balr%# r15,%0"
+  [(set_attr "type" "call")
+   (set_attr "length" "2")])
+
+(define_insn ""
+  [(call (mem:SI (match_operand:SI 0 "romp_symbolic_operand" "i"))
+	 (match_operand 1 "" "g"))
+   (clobber (reg:SI 15))]
+  "GET_CODE (operands[0]) == SYMBOL_REF"
+  "bali%# r15,%0"
+  [(set_attr "type" "call")])
+
+;; Call a function and return a value.
+(define_expand "call_value"
+  [(use (reg:SI 0))
+   (parallel [(set (match_operand 0 "" "=fg")
+		   (call (mem:SI (match_operand:SI 1 "address_operand" ""))
+			 (match_operand 2 "" "")))
+	      (clobber (reg:SI 15))])]
+  ""
+  "
+{
+  if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
+    abort();
+
+  operands[1] = XEXP (operands[1], 0);
+  if (GET_CODE (operands[1]) == SYMBOL_REF)
+    {
+      extern rtx get_symref ();
+      char *real_fcnname =
+		(char *) alloca (strlen (XSTR (operands[1], 0)) + 2);
+
+      /* Copy the data area address to r0.  */
+      emit_move_insn (gen_rtx (REG, SImode, 0),
+		      force_reg (SImode, operands[1]));
+      strcpy (real_fcnname, \".\");
+      strcat (real_fcnname, XSTR (operands[1], 0));
+      operands[1] = get_symref (real_fcnname);
+    }
+  else
+    {
+      rtx data_access;
+
+      emit_move_insn (gen_rtx (REG, SImode, 0),
+		      force_reg (SImode, operands[1]));
+      data_access = gen_rtx (MEM, SImode, operands[1]);
+      RTX_UNCHANGING_P (data_access) = 1;
+      operands[1] = copy_to_reg (data_access);
+    }
+}")
+
+(define_insn ""
+  [(set (match_operand 0 "" "=fg")
+	(call (mem:SI (match_operand:SI 1 "register_operand" "b"))
+	      (match_operand 2 "" "g")))
+   (clobber (reg:SI 15))]
+  ""
+  "balr%# r15,%1"
+  [(set_attr "length" "2")
+   (set_attr "type" "call")])
+
+(define_insn ""
+  [(set (match_operand 0 "" "=fg")
+	(call (mem:SI (match_operand:SI 1 "romp_symbolic_operand" "i"))
+	      (match_operand 2 "" "g")))
+   (clobber (reg:SI 15))]
+  "GET_CODE (operands[1]) == SYMBOL_REF"
+  "bali%# r15,%1"
+  [(set_attr "type" "call")])
+
+;; No operation insn.
+(define_insn "nop"
+  [(const_int 0)]
+  ""
+  "nopr r0"
+  [(set_attr "type" "address")
+   (set_attr "length" "2")
+   (set_attr "cc" "none")])
+
+;; Here are the floating-point operations.
+;;
+;; Start by providing DEFINE_EXPAND for each operation.
+;; The insns will be handled with MATCH_OPERATOR; the methodology will be
+;; discussed below.
+
+;; First the conversion operations.
+
+(define_expand "truncdfsf2"
+  [(parallel [(set (match_operand:SF 0 "general_operand" "")
+		   (float_truncate:SF (match_operand:DF 1 "general_operand" "")))
+	      (clobber (reg:SI 0))
+	      (clobber (reg:SI 15))])]
+  ""
+  "")
+
+(define_expand "extendsfdf2"
+  [(parallel [(set (match_operand:DF 0 "general_operand" "")
+		   (float_extend:DF (match_operand:SF 1 "general_operand" "")))
+	      (clobber (reg:SI 0))
+	      (clobber (reg:SI 15))])]
+  ""
+  "")
+
+(define_expand "floatsisf2"
+  [(parallel [(set (match_operand:SF 0 "general_operand" "")
+		   (float:SF (match_operand:SI 1 "general_operand" "")))
+	      (clobber (reg:SI 0))
+	      (clobber (reg:SI 15))])]
+  ""
+  "")
+
+(define_expand "floatsidf2"
+  [(parallel [(set (match_operand:DF 0 "general_operand" "")
+		   (float:DF (match_operand:SI 1 "general_operand" "")))
+	      (clobber (reg:SI 0))
+	      (clobber (reg:SI 15))])]
+  ""
+  "")
+
+(define_expand "fix_truncsfsi2"
+  [(parallel [(set (match_operand:SI 0 "general_operand" "")
+		   (fix:SI (match_operand:SF 1 "general_operand" "")))
+	      (clobber (reg:SI 0))
+	      (clobber (reg:SI 15))])]
+  ""
+  "")
+
+(define_expand "fix_truncdfsi2"
+  [(parallel [(set (match_operand:SI 0 "general_operand" "")
+		   (fix:SI (match_operand:DF 1 "general_operand" "")))
+	      (clobber (reg:SI 0))
+	      (clobber (reg:SI 15))])]
+  ""
+  "")
+
+;; Now the binary operations.
+
+(define_expand "addsf3"
+  [(parallel [(set (match_operand:SF 0 "general_operand" "")
+		   (plus:SF (match_operand:SF 1 "general_operand" "")
+			    (match_operand:SF 2 "general_operand" "")))
+	      (clobber (reg:SI 0))
+	      (clobber (reg:SI 15))])]
+  ""
+  "")
+
+(define_expand "adddf3"
+  [(parallel [(set (match_operand:DF 0 "general_operand" "")
+		   (plus:DF (match_operand:DF 1 "general_operand" "")
+			    (match_operand:DF 2 "general_operand" "")))
+	       (clobber (reg:SI 0))
+	       (clobber (reg:SI 15))])]
+  ""
+  "")
+
+(define_expand "subsf3"
+  [(parallel [(set (match_operand:SF 0 "general_operand" "")
+		   (minus:SF (match_operand:SF 1 "general_operand" "")
+			     (match_operand:SF 2 "general_operand" "")))
+	      (clobber (reg:SI 0))
+	      (clobber (reg:SI 15))])]
+  ""
+  "")
+
+(define_expand "subdf3"
+  [(parallel [(set (match_operand:DF 0 "general_operand" "")
+		   (minus:DF (match_operand:DF 1 "general_operand" "")
+			     (match_operand:DF 2 "general_operand" "")))
+	      (clobber (reg:SI 0))
+	      (clobber (reg:SI 15))])]
+  ""
+  "")
+
+(define_expand "mulsf3"
+  [(parallel [(set (match_operand:SF 0 "general_operand" "")
+		   (mult:SF (match_operand:SF 1 "general_operand" "")
+			    (match_operand:SF 2 "general_operand" "")))
+	      (clobber (reg:SI 0))
+	      (clobber (reg:SI 15))])]
+  ""
+  "")
+
+(define_expand "muldf3"
+  [(parallel [(set (match_operand:DF 0 "general_operand" "")
+		   (mult:DF (match_operand:DF 1 "general_operand" "")
+			    (match_operand:DF 2 "general_operand" "")))
+	      (clobber (reg:SI 0))
+	      (clobber (reg:SI 15))])]
+  ""
+  "")
+
+(define_expand "divsf3"
+  [(parallel [(set (match_operand:SF 0 "general_operand" "")
+		   (div:SF (match_operand:SF 1 "general_operand" "")
+			   (match_operand:SF 2 "general_operand" "")))
+	      (clobber (reg:SI 0))
+	      (clobber (reg:SI 15))])]
+  ""
+  "")
+
+(define_expand "divdf3"
+  [(parallel [(set (match_operand:DF 0 "general_operand" "")
+		   (div:DF (match_operand:DF 1 "general_operand" "")
+			   (match_operand:DF 2 "general_operand" "")))
+	      (clobber (reg:SI 0))
+	      (clobber (reg:SI 15))])]
+  ""
+  "")
+
+;; Unary floating-point operations.
+;;
+;; Negations can be done without floating-point, since this is IEEE.
+;; But we cannot do this if an operand is a hard FP register, since
+;; the SUBREG we create would not be valid.
+(define_expand "negsf2"
+  [(set (match_operand:SF 0 "register_operand" "")
+	(neg:SF (match_operand:SF 1 "register_operand" "")))]
+  ""
+  "
+{
+  if (! (GET_CODE (operands[0]) == REG
+	 && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
+	 && FP_REGNO_P (REGNO (operands[0])))
+      && ! (GET_CODE (operands[1]) == REG
+	    && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
+	    && FP_REGNO_P (REGNO (operands[1]))))
+    {
+      rtx result;
+      rtx target = operand_subword (operands[0], 0, 1, SFmode);
+
+      result = expand_binop (SImode, xor_optab,
+			     operand_subword_force (operands[1], 0, SFmode),
+			     gen_rtx (CONST_INT, VOIDmode, 0x80000000),
+			     target, 0, OPTAB_WIDEN);
+      if (result == 0)
+	abort ();
+
+      if (result != target)
+	emit_move_insn (result, target);
+
+      /* Make a place for REG_EQUAL.  */
+      emit_move_insn (operands[0], operands[0]);
+      DONE;
+    }
+}")
+
+(define_expand "negdf2"
+  [(set (match_operand:DF 0 "register_operand" "")
+	(neg:DF (match_operand:DF 1 "register_operand" "")))]
+  ""
+  "
+{
+  if (! (GET_CODE (operands[0]) == REG
+	 && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
+	 && FP_REGNO_P (REGNO (operands[0])))
+      && ! (GET_CODE (operands[1]) == REG
+	    && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
+	    && FP_REGNO_P (REGNO (operands[1]))))
+    {
+      rtx result;
+      rtx target = operand_subword (operands[0], 0, 1, DFmode);
+      rtx insns;
+
+      start_sequence ();
+      result = expand_binop (SImode, xor_optab,
+			     operand_subword_force (operands[1], 0, DFmode),
+			     gen_rtx (CONST_INT, VOIDmode, 0x80000000),
+			     target, 0, OPTAB_WIDEN);
+      if (result == 0)
+	abort ();
+
+      if (result != target)
+	emit_move_insn (result, target);
+  
+      emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
+		      operand_subword_force (operands[1], 1, DFmode));
+
+      insns = get_insns ();
+      end_sequence ();
+
+      emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
+      DONE;
+    }
+}")
+
+(define_expand "abssf2"
+  [(parallel [(set (match_operand:SF 0 "general_operand" "")
+		   (abs:SF (match_operand:SF 1 "general_operand" "")))
+	      (clobber (reg:SI 0))
+	      (clobber (reg:SI 15))])]
+  ""
+  "")
+
+(define_expand "absdf2"
+  [(parallel [(set (match_operand:DF 0 "general_operand" "")
+		   (abs:DF (match_operand:DF 1 "general_operand" "")))
+	      (clobber (reg:SI 0))
+	      (clobber (reg:SI 15))])]
+  ""
+  "")
+
+;; Any floating-point operation can be either SFmode or DFmode, and each
+;; operand (including the output) can be either a normal operand or a
+;; conversion from a normal operand.
+;;
+;; We use MATCH_OPERATOR to match a floating-point binary or unary operator
+;; and input and output conversions.  So we need 2^N patterns for each type
+;; of operation, where N is the number of operands, including the output.
+;; There are thus a total of 14 patterns, 8 for binary operations, 4 for
+;; unary operations and two for conversion/move operations (only one
+;; operand can have a conversion for move operations).  In addition, we have
+;; to be careful that a floating-point reload register doesn't get allocated
+;; for an integer.  We take care of this for inputs with PREFERRED_RELOAD_CLASS
+;; but need to have two different constraints for outputs.  This means that
+;; we have to duplicate each pattern where the output could be an integer.
+;; This adds another 7 patterns, for a total of 21.
+
+;; Start with conversion operations (moves are done above).
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=g")
+	(match_operator 1 "float_conversion"
+		[(match_operand 2 "general_operand" "frg")]))
+   (clobber (match_operand:SI 3 "reg_0_operand" "=&z"))
+   (clobber (match_operand:SI 4 "reg_15_operand" "=&t"))]
+  ""
+  "*
+{ return output_fpop (SET, operands[0], operands[2], 0, insn);
+}"
+  [(set_attr "type" "fp")])
+
+(define_insn ""
+  [(set (match_operand 0 "general_operand" "=frg")
+	(match_operator 1 "float_conversion"
+		[(match_operand 2 "general_operand" "frg")]))
+   (clobber (match_operand:SI 3 "reg_0_operand" "=&z"))
+   (clobber (match_operand:SI 4 "reg_15_operand" "=&t"))]
+  ""
+  "*
+{ return output_fpop (SET, operands[0], operands[2], 0, insn);
+}"
+  [(set_attr "type" "fp")])
+
+;; Next, binary floating-point operations.
+
+(define_insn ""
+  [(set (match_operand 0 "general_operand" "=frg")
+	(match_operator 1 "float_binary"
+		[(match_operand 2 "general_operand" "frg")
+		 (match_operand 3 "general_operand" "frg")]))
+   (clobber (match_operand:SI 4 "reg_0_operand" "=&z"))
+   (clobber (match_operand:SI 5 "reg_15_operand" "=&t"))]
+  "check_precision (GET_MODE (operands[1]), operands[2], operands[3])"
+  "*
+{ return output_fpop (GET_CODE (operands[1]), operands[0], 
+		      operands[2], operands[3], insn);
+}"
+  [(set_attr "type" "fp")])
+
+(define_insn ""
+  [(set (match_operand 0 "general_operand" "=frg")
+	(match_operator 1 "float_binary"
+		[(match_operand 2 "general_operand" "frg")
+		 (match_operator 3 "float_conversion"
+			[(match_operand 4 "general_operand" "frg")])]))
+   (clobber (match_operand:SI 5 "reg_0_operand" "=&z"))
+   (clobber (match_operand:SI 6 "reg_15_operand" "=&t"))]
+  "check_precision (GET_MODE (operands[1]), operands[2], operands[4])"
+  "*
+{ return output_fpop (GET_CODE (operands[1]), operands[0], 
+		      operands[2], operands[4], insn);
+}"
+  [(set_attr "type" "fp")])
+
+(define_insn ""
+  [(set (match_operand 0 "general_operand" "=frg")
+	(match_operator 1 "float_binary"
+		[(match_operator 2 "float_conversion"
+			[(match_operand 3 "general_operand" "frg")])
+		 (match_operand 4 "general_operand" "frg")]))
+   (clobber (match_operand:SI 5 "reg_0_operand" "=&z"))
+   (clobber (match_operand:SI 6 "reg_15_operand" "=&t"))]
+  "check_precision (GET_MODE (operands[1]), operands[3], operands[4])"
+  "*
+{ return output_fpop (GET_CODE (operands[1]), operands[0], 
+		      operands[3], operands[4], insn);
+}"
+  [(set_attr "type" "fp")])
+
+(define_insn ""
+  [(set (match_operand 0 "general_operand" "=frg")
+	(match_operator 1 "float_binary"
+		[(match_operator 2 "float_conversion"
+			[(match_operand 3 "general_operand" "frg")])
+		 (match_operator 4 "float_conversion"
+			[(match_operand 5 "general_operand" "frg")])]))
+   (clobber (match_operand:SI 6 "reg_0_operand" "=&z"))
+   (clobber (match_operand:SI 7 "reg_15_operand" "=&t"))]
+  "check_precision (GET_MODE (operands[1]), operands[3], operands[5])"
+  "*
+{ return output_fpop (GET_CODE (operands[1]), operands[0], 
+		      operands[3], operands[5], insn);
+}"
+  [(set_attr "type" "fp")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=g")
+	(match_operator 1 "float_conversion"
+		[(match_operator 2 "float_binary"
+			[(match_operand 3 "general_operand" "frg")
+			 (match_operand 4 "general_operand" "frg")])]))
+   (clobber (match_operand:SI 5 "reg_0_operand" "=&z"))
+   (clobber (match_operand:SI 6 "reg_15_operand" "=&t"))]
+  "check_precision (GET_MODE (operands[2]), operands[3], operands[4])"
+  "*
+{ return output_fpop (GET_CODE (operands[2]), operands[0], 
+		      operands[3], operands[4], insn);
+}"
+  [(set_attr "type" "fp")])
+
+(define_insn ""
+  [(set (match_operand 0 "general_operand" "=frg")
+	(match_operator 1 "float_conversion"
+		[(match_operator 2 "float_binary"
+			[(match_operand 3 "general_operand" "frg")
+			 (match_operand 4 "general_operand" "frg")])]))
+   (clobber (match_operand:SI 5 "reg_0_operand" "=&z"))
+   (clobber (match_operand:SI 6 "reg_15_operand" "=&t"))]
+  "check_precision (GET_MODE (operands[2]), operands[3], operands[4])"
+  "*
+{ return output_fpop (GET_CODE (operands[2]), operands[0], 
+		      operands[3], operands[4], insn);
+}"
+  [(set_attr "type" "fp")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=g")
+	(match_operator 1 "float_conversion"
+		[(match_operator 2 "float_binary"
+			[(match_operand 3 "general_operand" "frg")
+			 (match_operator 4 "float_conversion"
+			 	[(match_operand 5 "general_operand" "frg")])])]))
+   (clobber (match_operand:SI 6 "reg_0_operand" "=&z"))
+   (clobber (match_operand:SI 7 "reg_15_operand" "=&t"))]
+  "check_precision (GET_MODE (operands[2]), operands[3], operands[4])"
+  "*
+{ return output_fpop (GET_CODE (operands[2]), operands[0], 
+		      operands[3], operands[5], insn);
+}"
+  [(set_attr "type" "fp")])
+
+(define_insn ""
+  [(set (match_operand 0 "general_operand" "=frg")
+	(match_operator 1 "float_conversion"
+		[(match_operator 2 "float_binary"
+			[(match_operand 3 "general_operand" "frg")
+			 (match_operator 4 "float_conversion"
+			 	[(match_operand 5 "general_operand" "frg")])])]))
+   (clobber (match_operand:SI 6 "reg_0_operand" "=&z"))
+   (clobber (match_operand:SI 7 "reg_15_operand" "=&t"))]
+  "check_precision (GET_MODE (operands[2]), operands[3], operands[4])"
+  "*
+{ return output_fpop (GET_CODE (operands[2]), operands[0], 
+		      operands[3], operands[5], insn);
+}"
+  [(set_attr "type" "fp")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=g")
+	(match_operator 1 "float_conversion"
+		[(match_operator 2 "float_binary"
+			[(match_operator 3 "float_conversion"
+			 	[(match_operand 4 "general_operand" "frg")])
+			 (match_operand 5 "general_operand" "frg")])]))
+   (clobber (match_operand:SI 6 "reg_0_operand" "=&z"))
+   (clobber (match_operand:SI 7 "reg_15_operand" "=&t"))]
+  "check_precision (GET_MODE (operands[2]), operands[4], operands[5])"
+  "*
+{ return output_fpop (GET_CODE (operands[2]), operands[0], 
+		      operands[4], operands[5], insn);
+}"
+  [(set_attr "type" "fp")])
+
+(define_insn ""
+  [(set (match_operand 0 "general_operand" "=frg")
+	(match_operator 1 "float_conversion"
+		[(match_operator 2 "float_binary"
+			[(match_operator 3 "float_conversion"
+			 	[(match_operand 4 "general_operand" "frg")])
+			 (match_operand 5 "general_operand" "frg")])]))
+   (clobber (match_operand:SI 6 "reg_0_operand" "=&z"))
+   (clobber (match_operand:SI 7 "reg_15_operand" "=&t"))]
+  "check_precision (GET_MODE (operands[2]), operands[4], operands[5])"
+  "*
+{ return output_fpop (GET_CODE (operands[2]), operands[0], 
+		      operands[4], operands[5], insn);
+}"
+  [(set_attr "type" "fp")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=g")
+	(match_operator 1 "float_conversion"
+		[(match_operator 2 "float_binary"
+			[(match_operator 3 "float_conversion"
+			 	[(match_operand 4 "general_operand" "frg")])
+			 (match_operator 5 "float_conversion"
+			 	[(match_operand 6 "general_operand" "frg")])])]))
+   (clobber (match_operand:SI 7 "reg_0_operand" "=&z"))
+   (clobber (match_operand:SI 8 "reg_15_operand" "=&t"))]
+  "check_precision (GET_MODE (operands[2]), operands[4], operands[6])"
+  "*
+{ return output_fpop (GET_CODE (operands[2]), operands[0], 
+		      operands[4], operands[6], insn);
+}"
+  [(set_attr "type" "fp")])
+
+(define_insn ""
+  [(set (match_operand 0 "general_operand" "=frg")
+	(match_operator 1 "float_conversion"
+		[(match_operator 2 "float_binary"
+			[(match_operator 3 "float_conversion"
+			 	[(match_operand 4 "general_operand" "frg")])
+			 (match_operator 5 "float_conversion"
+			 	[(match_operand 6 "general_operand" "frg")])])]))
+   (clobber (match_operand:SI 7 "reg_0_operand" "=&z"))
+   (clobber (match_operand:SI 8 "reg_15_operand" "=&t"))]
+  "check_precision (GET_MODE (operands[2]), operands[4], operands[6])"
+  "*
+{ return output_fpop (GET_CODE (operands[2]), operands[0], 
+		      operands[4], operands[6], insn);
+}"
+  [(set_attr "type" "fp")])
+
+;; Unary floating-point operations.
+
+(define_insn ""
+  [(set (match_operand 0 "general_operand" "=frg")
+	(match_operator 1 "float_unary"
+		[(match_operand 2 "general_operand" "frg")]))
+   (clobber (match_operand:SI 3 "reg_0_operand" "=&z"))
+   (clobber (match_operand:SI 4 "reg_15_operand" "=&t"))]
+  "check_precision (GET_MODE (operands[1]), operands[2], 0)"
+  "*
+{ return output_fpop (GET_CODE (operands[1]), operands[0], operands[2],
+		      0, insn);
+}"
+  [(set_attr "type" "fp")])
+
+(define_insn ""
+  [(set (match_operand 0 "general_operand" "=frg")
+	(match_operator 1 "float_unary"
+		[(match_operator 2 "float_conversion"
+			[(match_operand 3 "general_operand" "frg")])]))
+   (clobber (match_operand:SI 4 "reg_0_operand" "=&z"))
+   (clobber (match_operand:SI 5 "reg_15_operand" "=&t"))]
+  "check_precision (GET_MODE (operands[1]), operands[3], 0)"
+  "*
+{ return output_fpop (GET_CODE (operands[1]), operands[0], operands[3],
+		      0, insn);
+}"
+  [(set_attr "type" "fp")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=g")
+	(match_operator 1 "float_conversion"
+		[(match_operator 2 "float_unary"
+			[(match_operand 3 "general_operand" "frg")])]))
+   (clobber (match_operand:SI 4 "reg_0_operand" "=&z"))
+   (clobber (match_operand:SI 5 "reg_15_operand" "=&t"))]
+  "check_precision (GET_MODE (operands[2]), operands[3], 0)"
+  "*
+{ return output_fpop (GET_CODE (operands[2]), operands[0], operands[3],
+		      0, insn);
+}"
+  [(set_attr "type" "fp")])
+
+(define_insn ""
+  [(set (match_operand 0 "general_operand" "=frg")
+	(match_operator 1 "float_conversion"
+		[(match_operator 2 "float_unary"
+			[(match_operand 3 "general_operand" "frg")])]))
+   (clobber (match_operand:SI 4 "reg_0_operand" "=&z"))
+   (clobber (match_operand:SI 5 "reg_15_operand" "=&t"))]
+  "check_precision (GET_MODE (operands[2]), operands[3], 0)"
+  "*
+{ return output_fpop (GET_CODE (operands[2]), operands[0], operands[3],
+		      0, insn);
+}"
+  [(set_attr "type" "fp")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=g")
+	(match_operator 1 "float_conversion"
+		[(match_operator 2 "float_unary"
+			[(match_operator 3 "float_conversion"
+			 	[(match_operand 4 "general_operand" "frg")])])]))
+   (clobber (match_operand:SI 5 "reg_0_operand" "=&z"))
+   (clobber (match_operand:SI 6 "reg_15_operand" "=&t"))]
+  "check_precision (GET_MODE (operands[2]), operands[4], 0)"
+  "*
+{ return output_fpop (GET_CODE (operands[2]), operands[0], operands[4],
+		      0, insn);
+}"
+  [(set_attr "type" "fp")])
+
+(define_insn ""
+  [(set (match_operand 0 "general_operand" "=frg")
+	(match_operator 1 "float_conversion"
+		[(match_operator 2 "float_unary"
+			[(match_operator 3 "float_conversion"
+			 	[(match_operand 4 "general_operand" "frg")])])]))
+   (clobber (match_operand:SI 5 "reg_0_operand" "=&z"))
+   (clobber (match_operand:SI 6 "reg_15_operand" "=&t"))]
+  "check_precision (GET_MODE (operands[2]), operands[4], 0)"
+  "*
+{ return output_fpop (GET_CODE (operands[2]), operands[0], operands[4],
+		      0, insn);
+}"
+  [(set_attr "type" "fp")])
+
+;; Compare insns are next.  Note that the ROMP has two types of compares,
+;; signed & unsigned, and one type of branch.  Use the routine
+;; `next_insn_tests_no_unsigned' to see which type to use.
+(define_expand "tstsi"
+  [(set (cc0)
+	(match_operand:SI 0 "register_operand" "r"))]
+  ""
+  "")
+
+(define_expand "cmpsi"
+  [(set (cc0)
+        (compare (match_operand:SI 0 "register_operand" "")
+  		 (match_operand:SI 1 "reg_or_cint_operand" "")))]
+  ""
+  "")
+
+;; Signed compare, `test' first.
+
+(define_insn ""
+  [(set (cc0)
+	(match_operand:SI 0 "register_operand" "r"))]
+  "next_insn_tests_no_unsigned (insn)"
+  "cis %0,0"
+  [(set_attr "length" "2")
+   (set_attr "type" "compare")])
+
+(define_insn ""
+  [(set (cc0) (match_operand:SI 0 "register_operand" "r,r,r"))
+   (set (match_operand:SI 1 "reg_or_nonsymb_mem_operand" "=0,r,Q")
+	(match_dup 0))]
+  "next_insn_tests_no_unsigned (insn)"
+  "@
+   cis %1,0
+   nilo %1,%0,65535
+   st%M1 %0,%1\;cis %0,0"
+  [(set_attr "type" "compare,compare,store")
+   (set_attr "length" "2,4,6")
+   (set_attr "cc" "compare")])
+
+(define_insn ""
+  [(set (cc0)
+        (compare (match_operand:SI 0 "register_operand" "r,r,r")
+		 (match_operand:SI 1 "reg_or_cint_operand" "I,K,r")))]
+  "next_insn_tests_no_unsigned (insn)"
+  "@
+   cis %0,%1
+   cil %0,%1
+   c %0,%1"
+  [(set_attr "length" "2,4,2")
+   (set_attr "type" "compare")])
+
+;; Unsigned comparisons, `test' first, again.
+(define_insn ""
+  [(set (cc0)
+	(match_operand:SI 0 "register_operand" "r"))]
+  "! next_insn_tests_no_unsigned (insn)"
+  "clil %0,0"
+  [(set_attr "type" "compare")])
+
+(define_insn ""
+  [(set (cc0)
+        (compare (match_operand:SI 0 "register_operand" "r,r")
+		 (match_operand:SI 1 "reg_or_cint_operand" "K,r")))]
+  "! next_insn_tests_no_unsigned (insn)"
+  "@
+   clil %0,%1
+   cl %0,%1"
+  [(set_attr "length" "4,2")
+   (set_attr "type" "compare")])
+
+;; Bit test insn.  Many cases are converted into this by combine.  This
+;; uses the ROMP test bit.
+
+(define_insn ""
+  [(set (cc0)
+	(zero_extract (match_operand:SI 0 "register_operand" "r,r")
+		      (const_int 1)
+		      (match_operand:SI 1 "reg_or_any_cint_operand" "r,n")))]
+  "next_insn_tests_no_inequality (insn)"
+  "@
+   mttb %0,%1
+   mttbi%t1 %0,%S1"
+  [(set_attr "length" "2")
+   (set_attr "type" "compare")
+   (set_attr "cc" "tbit")])
+
+;; Floating-point comparisons.  There are two, equality and order.
+;; The difference will be that a trap for NaN will be given on the orderr
+;; comparisons only.
+
+(define_expand "cmpsf"
+  [(parallel [(set (cc0) (compare (match_operand:SF 0 "general_operand" "")
+				  (match_operand:SF 1 "general_operand" "")))
+	      (clobber (reg:SI 0))
+	      (clobber (reg:SI 15))])]
+  ""
+  "")
+
+(define_expand "cmpdf"
+  [(parallel [(set (cc0) (compare (match_operand:DF 0 "general_operand" "")
+				  (match_operand:DF 1 "general_operand" "")))
+	      (clobber (reg:SI 0))
+	      (clobber (reg:SI 15))])]
+  ""
+  "")
+
+(define_expand "tstsf"
+  [(parallel [(set (cc0) (match_operand:SF 0 "general_operand" ""))
+	      (clobber (reg:SI 0))
+	      (clobber (reg:SI 15))])]
+  ""
+  "")
+
+(define_expand "tstdf"
+  [(parallel [(set (cc0) (match_operand:DF 0 "general_operand" ""))
+	      (clobber (reg:SI 0))
+	      (clobber (reg:SI 15))])]
+  ""
+  "")
+
+;; There are four cases for compare and two for test.  These correspond
+;; to each input having a floating-point conversion or not.
+
+(define_insn ""
+  [(set (cc0) (compare (match_operand 0 "general_operand" "frg")
+		       (match_operand 1 "general_operand" "frg")))
+   (clobber (match_operand:SI 2 "reg_0_operand" "=&z"))
+   (clobber (match_operand:SI 3 "reg_15_operand" "=&t"))]
+  "GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode"
+  "*
+{ return output_fpop (next_insn_tests_no_inequality (insn) ? EQ : GE,
+		      operands[0], operands[1], 0, insn);
+}"
+  [(set_attr "type" "fp")
+   (set_attr "cc" "compare")])
+
+(define_insn ""
+  [(set (cc0) (compare (match_operand 0 "general_operand" "frg")
+		       (match_operator 1 "float_conversion"
+			      [(match_operand 2 "general_operand" "frg")])))
+   (clobber (match_operand:SI 3 "reg_0_operand" "=&z"))
+   (clobber (match_operand:SI 4 "reg_15_operand" "=&t"))]
+  ""
+  "*
+{ return output_fpop (next_insn_tests_no_inequality (insn) ? EQ : GE,
+		      operands[0], operands[2], 0, insn);
+}"
+  [(set_attr "type" "fp")
+   (set_attr "cc" "compare")])
+
+(define_insn ""
+  [(set (cc0) (compare (match_operator 0 "float_conversion"
+			      [(match_operand 1 "general_operand" "frg")])
+		       (match_operand 2 "general_operand" "frg")))
+   (clobber (match_operand:SI 3 "reg_0_operand" "=&z"))
+   (clobber (match_operand:SI 4 "reg_15_operand" "=&t"))]
+  ""
+  "*
+{ return output_fpop (next_insn_tests_no_inequality (insn) ? EQ : GE,
+		      operands[1], operands[2], 0, insn);
+}"
+  [(set_attr "type" "fp")
+   (set_attr "cc" "compare")])
+
+(define_insn ""
+  [(set (cc0) (compare (match_operator 0 "float_conversion"
+			      [(match_operand 1 "general_operand" "frg")])
+		       (match_operator 2 "float_conversion"
+			      [(match_operand 3 "general_operand" "frg")])))
+   (clobber (match_operand:SI 4 "reg_0_operand" "=&z"))
+   (clobber (match_operand:SI 5 "reg_15_operand" "=&t"))]
+  ""
+  "*
+{ return output_fpop (next_insn_tests_no_inequality (insn) ? EQ : GE,
+		      operands[1], operands[3], 0, insn);
+}"
+  [(set_attr "type" "fp")
+   (set_attr "cc" "compare")])
+
+(define_insn ""
+  [(set (cc0) (match_operand 0 "general_operand" "frg"))
+   (clobber (match_operand:SI 1 "reg_0_operand" "=&z"))
+   (clobber (match_operand:SI 2 "reg_15_operand" "=&t"))]
+  "GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode"
+  "*
+{ return output_fpop (next_insn_tests_no_inequality (insn) ? EQ : GE,
+		      operands[0], immed_real_const_1 (0, 0,
+						       GET_MODE (operands[0])),
+		      0, insn);
+}"
+  [(set_attr "type" "fp")
+   (set_attr "cc" "compare")])
+
+(define_insn ""
+  [(set (cc0) (match_operator 0 "float_conversion"
+			[(match_operand 1 "general_operand" "frg")]))
+   (clobber (match_operand:SI 2 "reg_0_operand" "=&z"))
+   (clobber (match_operand:SI 3 "reg_15_operand" "=&t"))]
+  ""
+  "*
+{ return output_fpop (next_insn_tests_no_inequality (insn) ? EQ : GE,
+		      operands[1], immed_real_const_1 (0, 0,
+						       GET_MODE (operands[1])),
+		      0, insn);
+}"
+  [(set_attr "type" "fp")
+   (set_attr "cc" "compare")])
+
+;; Branch insns.  Unsigned vs. signed have already
+;; been taken care of.  The only insns that need to be concerned about the
+;; test bit are beq and bne because the rest are either always true,
+;; always false, or converted to EQ or NE.
+
+;; For conditional branches, we use `define_expand' and just have two patterns
+;; that match them.  Operand printing does most of the work.
+
+(define_expand "beq"
+  [(set (pc)
+	(if_then_else (eq (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "")
+
+(define_expand "bne"
+  [(set (pc)
+	(if_then_else (ne (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "")
+
+(define_expand "bgt"
+  [(set (pc)
+	(if_then_else (gt (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "")
+
+(define_expand "bgtu"
+  [(set (pc)
+	(if_then_else (gtu (cc0)
+			   (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "")
+
+(define_expand "blt"
+  [(set (pc)
+	(if_then_else (lt (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "")
+
+(define_expand "bltu"
+  [(set (pc)
+	(if_then_else (ltu (cc0)
+			   (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "")
+
+(define_expand "bge"
+  [(set (pc)
+	(if_then_else (ge (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "")
+
+(define_expand "bgeu"
+  [(set (pc)
+	(if_then_else (geu (cc0)
+			   (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "")
+
+(define_expand "ble"
+  [(set (pc)
+	(if_then_else (le (cc0)
+			  (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "")
+
+(define_expand "bleu"
+  [(set (pc)
+	(if_then_else (leu (cc0)
+			   (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "")
+
+;; Define both directions of branch and return.
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (match_operator 1 "comparison_operator"
+				      [(cc0) (const_int 0)])
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "*
+{
+  if (restore_compare_p (operands[1]))
+    return 0;
+  else if (get_attr_length (insn) == 2)
+    return \"j%j1 %l0\";
+  else
+    return \"b%j1%# %l0\";
+}"
+  [(set_attr "type" "branch")])
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (match_operator 0 "comparison_operator"
+				      [(cc0) (const_int 0)])
+		      (return)
+		      (pc)))]
+  "null_epilogue ()"
+  "*
+{
+  if (restore_compare_p (operands[0]))
+    return 0;
+  else
+    return \"b%j0r%# r15\";
+}"
+  [(set_attr "type" "return")])
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (match_operator 1 "comparison_operator"
+				[(cc0) (const_int 0)])
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "*
+{
+  if (restore_compare_p (operands[1]))
+    return 0;
+  else if (get_attr_length (insn) == 2)
+    return \"j%J1 %l0\";
+  else
+    return \"b%J1%# %l0\";
+}"
+  [(set_attr "type" "branch")])
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (match_operator 0 "comparison_operator"
+				      [(cc0) (const_int 0)])
+		      (pc)
+		      (return)))]
+  "null_epilogue ()"
+  "*
+{
+  if (restore_compare_p (operands[0]))
+    return 0;
+  else
+    return \"b%J0r%# r15\";
+}"
+  [(set_attr "type" "return")])
+
+;; Unconditional branch and return.
+
+(define_insn "jump"
+  [(set (pc)
+	(label_ref (match_operand 0 "" "")))]
+  ""
+  "*
+{
+  if (get_attr_length (insn) == 2)
+    return \"j %l0\";
+  else
+    return \"b%# %l0\";
+}"
+  [(set_attr "type" "branch")])
+
+(define_insn "return"
+  [(return)]
+  "null_epilogue ()"
+  "br%# r15"
+  [(set_attr "type" "return")])
+
+(define_insn "indirect_jump"
+  [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
+  ""
+  "br%# %0"
+  [(set_attr "type" "branch")
+   (set_attr "length" "2")])
+
+;; Table jump for switch statements:
+(define_insn "tablejump"
+  [(set (pc)
+	(match_operand:SI 0 "register_operand" "r"))
+   (use (label_ref (match_operand 1 "" "")))]
+  ""
+  "br%# %0"
+  [(set_attr "type" "branch")
+   (set_attr "length" "2")])
+
+;;- Local variables:
+;;- mode:emacs-lisp
+;;- comment-start: ";;- "
+;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
+;;- eval: (modify-syntax-entry ?[ "(]")
+;;- eval: (modify-syntax-entry ?] ")[")
+;;- eval: (modify-syntax-entry ?{ "(}")
+;;- eval: (modify-syntax-entry ?} "){")
+;;- End: