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authorzhongjuzhe <juzhe.zhong@rivai.ai>2022-09-15 16:28:53 +0800
committerKito Cheng <kito.cheng@sifive.com>2022-09-23 23:33:24 +0800
commitb4feb49cf308b344fba6a72137df58de382fcb9d (patch)
treecbabdb92309bbf9f1538bcb7a811c16b8ee66357 /gcc/config/riscv/t-riscv
parentab98b4c0725eb7c0f03d319ef3e22ae761b2698a (diff)
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RISC-V: Support poly move manipulation and selftests.
gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Change "static void" to "void". * config.gcc: Add riscv-selftests.o * config/riscv/predicates.md: Allow const_poly_int. * config/riscv/riscv-protos.h (riscv_reinit): New function. (riscv_parse_arch_string): change as exten function. (riscv_run_selftests): New function. * config/riscv/riscv.cc (riscv_cannot_force_const_mem): Don't allow poly into const pool. (riscv_report_v_required): New function. (riscv_expand_op): New function. (riscv_expand_mult_with_const_int): New function. (riscv_legitimize_poly_move): Ditto. (riscv_legitimize_move): New function. (riscv_hard_regno_mode_ok): Add VL/VTYPE register allocation and fix vector RA. (riscv_convert_vector_bits): Fix riscv_vector_chunks configuration for -marh no 'v'. (riscv_reinit): New function. (TARGET_RUN_TARGET_SELFTESTS): New target hook support. * config/riscv/t-riscv: Add riscv-selftests.o. * config/riscv/riscv-selftests.cc: New file. gcc/testsuite/ChangeLog: * selftests/riscv/empty-func.rtl: New test.
Diffstat (limited to 'gcc/config/riscv/t-riscv')
-rw-r--r--gcc/config/riscv/t-riscv4
1 files changed, 4 insertions, 0 deletions
diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv
index 19736b3..2b82e5f 100644
--- a/gcc/config/riscv/t-riscv
+++ b/gcc/config/riscv/t-riscv
@@ -23,6 +23,10 @@ riscv-shorten-memrefs.o: $(srcdir)/config/riscv/riscv-shorten-memrefs.cc
$(COMPILE) $<
$(POSTCOMPILE)
+riscv-selftests.o: $(srcdir)/config/riscv/riscv-selftests.cc
+ $(COMPILE) $<
+ $(POSTCOMPILE)
+
PASSES_EXTRA += $(srcdir)/config/riscv/riscv-passes.def
$(common_out_file): $(srcdir)/config/riscv/riscv-cores.def \