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| author | Pan Li <pan2.li@intel.com> | 2023-08-17 15:21:42 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-08-17 15:37:57 +0800 |
| commit | c6259c4975e84b30d7de1f64afaece614d7c4500 (patch) | |
| tree | 7fb33e487e7bd3b1e1f95fd5f488192ecbd74b7b /gcc/config/riscv/riscv-vector-builtins-bases.h | |
| parent | 3a68ef2cccb8a7f15ca188dbffd754d112d75898 (diff) | |
| download | gcc-c6259c4975e84b30d7de1f64afaece614d7c4500.zip gcc-c6259c4975e84b30d7de1f64afaece614d7c4500.tar.gz gcc-c6259c4975e84b30d7de1f64afaece614d7c4500.tar.bz2 | |
RISC-V: Support RVV VFWREDOSUM.VS rounding mode intrinsic API
This patch would like to support the rounding mode API for the
VFWREDOSUM.VS as the below samples
* __riscv_vfwredosum_vs_f32m1_f64m1_rm
* __riscv_vfwredosum_vs_f32m1_f64m1_rm_m
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(widen_freducop): Add frm_opt_type template arg.
(vfwredosum_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfwredosum_frm): New intrinsic function def.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-wredosum.c: New test.
Diffstat (limited to 'gcc/config/riscv/riscv-vector-builtins-bases.h')
| -rw-r--r-- | gcc/config/riscv/riscv-vector-builtins-bases.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index da8412b..c1bb164 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -245,6 +245,7 @@ extern const function_base *const vfredosum_frm; extern const function_base *const vfredmax; extern const function_base *const vfredmin; extern const function_base *const vfwredosum; +extern const function_base *const vfwredosum_frm; extern const function_base *const vfwredusum; extern const function_base *const vmv_x; extern const function_base *const vmv_s; |