diff options
| author | Pan Li <pan2.li@intel.com> | 2023-08-04 10:55:09 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-08-04 14:02:41 +0800 |
| commit | dccd7e8a7215f3f2e295e11b20680d3add08cd7e (patch) | |
| tree | aaf3c31ea39fe9cd96106e07581f3516848c01eb /gcc/config/riscv/riscv-vector-builtins-bases.cc | |
| parent | 62d9c1dd8eb1152d8fbe0e1df101b99c9141417a (diff) | |
| download | gcc-dccd7e8a7215f3f2e295e11b20680d3add08cd7e.zip gcc-dccd7e8a7215f3f2e295e11b20680d3add08cd7e.tar.gz gcc-dccd7e8a7215f3f2e295e11b20680d3add08cd7e.tar.bz2 | |
RISC-V: Support RVV VFMSAC rounding mode intrinsic API
This patch would like to support the rounding mode API for the
VFMSAC for the below samples.
* __riscv_vfmsac_vv_f32m1_rm
* __riscv_vfmsac_vv_f32m1_rm_m
* __riscv_vfmsac_vf_f32m1_rm
* __riscv_vfmsac_vf_f32m1_rm_m
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfmsac_frm): New class for vfmsac frm.
(vfmsac_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfmsac_frm): New function definition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-single-multiply-sub.c: New test.
Diffstat (limited to 'gcc/config/riscv/riscv-vector-builtins-bases.cc')
| -rw-r--r-- | gcc/config/riscv/riscv-vector-builtins-bases.cc | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 1d4a5a1..e73051b 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -401,6 +401,28 @@ public: } }; +/* Implements below instructions for frm + - vfmsac +*/ +class vfmsac_frm : public function_base +{ +public: + bool has_rounding_mode_operand_p () const override { return true; } + + bool has_merge_operand_p () const override { return false; } + + rtx expand (function_expander &e) const override + { + if (e.op_info->op == OP_TYPE_vf) + return e.use_ternop_insn ( + true, code_for_pred_mul_scalar (MINUS, e.vector_mode ())); + if (e.op_info->op == OP_TYPE_vv) + return e.use_ternop_insn ( + true, code_for_pred_mul (MINUS, e.vector_mode ())); + gcc_unreachable (); + } +}; + /* Implements vrsub. */ class vrsub : public function_base { @@ -2168,6 +2190,7 @@ static CONSTEXPR const vfnmsub vfnmsub_obj; static CONSTEXPR const vfnmacc vfnmacc_obj; static CONSTEXPR const vfnmacc_frm vfnmacc_frm_obj; static CONSTEXPR const vfmsac vfmsac_obj; +static CONSTEXPR const vfmsac_frm vfmsac_frm_obj; static CONSTEXPR const vfnmadd vfnmadd_obj; static CONSTEXPR const vfmsub vfmsub_obj; static CONSTEXPR const vfwmacc vfwmacc_obj; @@ -2405,6 +2428,7 @@ BASE (vfnmsub) BASE (vfnmacc) BASE (vfnmacc_frm) BASE (vfmsac) +BASE (vfmsac_frm) BASE (vfnmadd) BASE (vfmsub) BASE (vfwmacc) |