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| author | Pan Li <pan2.li@intel.com> | 2023-08-14 14:03:29 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-08-14 15:08:36 +0800 |
| commit | c944ded09595946290778a26794074e69cc65f3e (patch) | |
| tree | 82a7686d46d9f8cf76f47e6b7ce923e09327909c /gcc/config/riscv/riscv-vector-builtins-bases.cc | |
| parent | d9577b4b4c2a7b4e8bc869d33b7de98a0e507e7c (diff) | |
| download | gcc-c944ded09595946290778a26794074e69cc65f3e.zip gcc-c944ded09595946290778a26794074e69cc65f3e.tar.gz gcc-c944ded09595946290778a26794074e69cc65f3e.tar.bz2 | |
RISC-V: Support RVV VFWNMSAC rounding mode intrinsic API
This patch would like to support the rounding mode API for the
VFWNMSAC as the below samples.
* __riscv_vfwnmsac_vv_f64m2_rm
* __riscv_vfwnmsac_vv_f64m2_rm_m
* __riscv_vfwnmsac_vf_f64m2_rm
* __riscv_vfwnmsac_vf_f64m2_rm_m
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfwnmsac_frm): New class for frm.
(vfwnmsac_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfwnmsac_frm): New intrinsic function definition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-wnmsac.c: New test.
Diffstat (limited to 'gcc/config/riscv/riscv-vector-builtins-bases.cc')
| -rw-r--r-- | gcc/config/riscv/riscv-vector-builtins-bases.cc | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 5a5da90..b458560 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -608,6 +608,29 @@ public: } }; +/* Implements below instructions for frm + - vfwnmsac +*/ +class vfwnmsac_frm : public function_base +{ +public: + bool has_rounding_mode_operand_p () const override { return true; } + + bool has_merge_operand_p () const override { return false; } + + rtx expand (function_expander &e) const override + { + if (e.op_info->op == OP_TYPE_vf) + return e.use_widen_ternop_insn ( + code_for_pred_widen_mul_neg_scalar (PLUS, e.vector_mode ())); + if (e.op_info->op == OP_TYPE_vv) + return e.use_widen_ternop_insn ( + code_for_pred_widen_mul_neg (PLUS, e.vector_mode ())); + + gcc_unreachable (); + } +}; + /* Implements vrsub. */ class vrsub : public function_base { @@ -2390,6 +2413,7 @@ static CONSTEXPR const vfwnmacc_frm vfwnmacc_frm_obj; static CONSTEXPR const vfwmsac vfwmsac_obj; static CONSTEXPR const vfwmsac_frm vfwmsac_frm_obj; static CONSTEXPR const vfwnmsac vfwnmsac_obj; +static CONSTEXPR const vfwnmsac_frm vfwnmsac_frm_obj; static CONSTEXPR const unop<SQRT> vfsqrt_obj; static CONSTEXPR const float_misc<UNSPEC_VFRSQRT7> vfrsqrt7_obj; static CONSTEXPR const float_misc<UNSPEC_VFREC7> vfrec7_obj; @@ -2636,6 +2660,7 @@ BASE (vfwnmacc_frm) BASE (vfwmsac) BASE (vfwmsac_frm) BASE (vfwnmsac) +BASE (vfwnmsac_frm) BASE (vfsqrt) BASE (vfrsqrt7) BASE (vfrec7) |