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| author | Pan Li <pan2.li@intel.com> | 2023-08-16 13:15:04 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-08-16 13:59:43 +0800 |
| commit | c6f65ce9483131b1996cbddf8aaaebe0d8e5141c (patch) | |
| tree | 5f89e3dcb9804aecf8db0b288e7db11ff59cee04 /gcc/config/riscv/riscv-vector-builtins-bases.cc | |
| parent | b2a927fb5343db363ea4361da0d6bcee227b6737 (diff) | |
| download | gcc-c6f65ce9483131b1996cbddf8aaaebe0d8e5141c.zip gcc-c6f65ce9483131b1996cbddf8aaaebe0d8e5141c.tar.gz gcc-c6f65ce9483131b1996cbddf8aaaebe0d8e5141c.tar.bz2 | |
RISC-V: Support RVV VFCVT.X.F.V rounding mode intrinsic API
This patch would like to support the rounding mode API for the
VFCVT.X.F.V as the below samples.
* __riscv_vfcvt_x_f_v_i32m1_rm
* __riscv_vfcvt_x_f_v_i32m1_rm_m
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(enum frm_op_type): New type for frm.
(BASE): New declaration.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfcvt_x_frm): New intrinsic function def.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-cvt-x.c: New test.
Diffstat (limited to 'gcc/config/riscv/riscv-vector-builtins-bases.cc')
| -rw-r--r-- | gcc/config/riscv/riscv-vector-builtins-bases.cc | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index f212408..817d2ed 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -58,6 +58,12 @@ enum lst_type LST_INDEXED, }; +enum frm_op_type +{ + NO_FRM, + HAS_FRM, +}; + /* Helper function to fold vleff and vlsegff. */ static gimple * fold_fault_load (gimple_folder &f) @@ -1662,10 +1668,15 @@ public: }; /* Implements vfcvt.x. */ -template<int UNSPEC> +template<int UNSPEC, enum frm_op_type FRM_OP = NO_FRM> class vfcvt_x : public function_base { public: + bool has_rounding_mode_operand_p () const override + { + return FRM_OP == HAS_FRM; + } + rtx expand (function_expander &e) const override { return e.use_exact_insn (code_for_pred_fcvt_x_f (UNSPEC, e.arg_mode (0))); @@ -2465,6 +2476,7 @@ static CONSTEXPR const vfclass vfclass_obj; static CONSTEXPR const vmerge vfmerge_obj; static CONSTEXPR const vmv_v vfmv_v_obj; static CONSTEXPR const vfcvt_x<UNSPEC_VFCVT> vfcvt_x_obj; +static CONSTEXPR const vfcvt_x<UNSPEC_VFCVT, HAS_FRM> vfcvt_x_frm_obj; static CONSTEXPR const vfcvt_x<UNSPEC_UNSIGNED_VFCVT> vfcvt_xu_obj; static CONSTEXPR const vfcvt_rtz_x<FIX> vfcvt_rtz_x_obj; static CONSTEXPR const vfcvt_rtz_x<UNSIGNED_FIX> vfcvt_rtz_xu_obj; @@ -2714,6 +2726,7 @@ BASE (vfclass) BASE (vfmerge) BASE (vfmv_v) BASE (vfcvt_x) +BASE (vfcvt_x_frm) BASE (vfcvt_xu) BASE (vfcvt_rtz_x) BASE (vfcvt_rtz_xu) |