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| author | Pan Li <pan2.li@intel.com> | 2023-08-16 20:47:38 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-08-17 15:32:32 +0800 |
| commit | 3d18a528bfd05f0bfdb27f52c2f6c2445f15e4ca (patch) | |
| tree | 151a23fcd165bc67d1bac286376c73dd1321f423 /gcc/config/riscv/riscv-vector-builtins-bases.cc | |
| parent | 5ccdfd0870be168031f8902e1039e77be93b131a (diff) | |
| download | gcc-3d18a528bfd05f0bfdb27f52c2f6c2445f15e4ca.zip gcc-3d18a528bfd05f0bfdb27f52c2f6c2445f15e4ca.tar.gz gcc-3d18a528bfd05f0bfdb27f52c2f6c2445f15e4ca.tar.bz2 | |
RISC-V: Support RVV VFNCVT.X.F.W rounding mode intrinsic API
This patch would like to support the rounding mode API for the
VFNCVT.X.F.W as the below samples.
* __riscv_vfncvt_x_f_w_i16mf2_rm
* __riscv_vfncvt_x_f_w_i16mf2_rm_m
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfncvt_x): Add frm_op_type template arg.
(BASE): New declaration.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfncvt_x_frm): New intrinsic function def.
* config/riscv/riscv-vector-builtins-shapes.cc
(struct narrow_alu_frm_def): New shape function for frm.
(SHAPE): New declaration.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-ncvt-x.c: New test.
Diffstat (limited to 'gcc/config/riscv/riscv-vector-builtins-bases.cc')
| -rw-r--r-- | gcc/config/riscv/riscv-vector-builtins-bases.cc | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 050ecbe..2f40eea 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -1759,10 +1759,15 @@ public: }; /* Implements vfncvt.x. */ -template<int UNSPEC> +template<int UNSPEC, enum frm_op_type FRM_OP = NO_FRM> class vfncvt_x : public function_base { public: + bool has_rounding_mode_operand_p () const override + { + return FRM_OP == HAS_FRM; + } + rtx expand (function_expander &e) const override { return e.use_exact_insn ( @@ -2502,6 +2507,7 @@ static CONSTEXPR const vfwcvt_rtz_x<FIX> vfwcvt_rtz_x_obj; static CONSTEXPR const vfwcvt_rtz_x<UNSIGNED_FIX> vfwcvt_rtz_xu_obj; static CONSTEXPR const vfwcvt_f vfwcvt_f_obj; static CONSTEXPR const vfncvt_x<UNSPEC_VFCVT> vfncvt_x_obj; +static CONSTEXPR const vfncvt_x<UNSPEC_VFCVT, HAS_FRM> vfncvt_x_frm_obj; static CONSTEXPR const vfncvt_x<UNSPEC_UNSIGNED_VFCVT> vfncvt_xu_obj; static CONSTEXPR const vfncvt_rtz_x<FIX> vfncvt_rtz_x_obj; static CONSTEXPR const vfncvt_rtz_x<UNSIGNED_FIX> vfncvt_rtz_xu_obj; @@ -2756,6 +2762,7 @@ BASE (vfwcvt_rtz_x) BASE (vfwcvt_rtz_xu) BASE (vfwcvt_f) BASE (vfncvt_x) +BASE (vfncvt_x_frm) BASE (vfncvt_xu) BASE (vfncvt_rtz_x) BASE (vfncvt_rtz_xu) |