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| author | Pan Li <pan2.li@intel.com> | 2023-08-17 16:03:20 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-08-22 08:00:51 +0800 |
| commit | 1d17e3d66736cc8d875bf02530f3f6aa498f0d09 (patch) | |
| tree | 915158a864308427eedb407f0a0f0ad61d2e7030 /gcc/config/riscv/riscv-vector-builtins-bases.cc | |
| parent | e2c42860b6bad30bad8dd12fd0e25dc55646a69c (diff) | |
| download | gcc-1d17e3d66736cc8d875bf02530f3f6aa498f0d09.zip gcc-1d17e3d66736cc8d875bf02530f3f6aa498f0d09.tar.gz gcc-1d17e3d66736cc8d875bf02530f3f6aa498f0d09.tar.bz2 | |
RISC-V: Support RVV VFWREDUSUM.VS rounding mode intrinsic API
This patch would like to support the rounding mode API for the
VFWREDUSUM.VS as the below samples
* __riscv_vfwredusum_vs_f32m1_f64m1_rm
* __riscv_vfwredusum_vs_f32m1_f64m1_rm_m
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(vfwredusum_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfwredusum_frm): New intrinsic function def.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-wredusum.c: New test.
Diffstat (limited to 'gcc/config/riscv/riscv-vector-builtins-bases.cc')
| -rw-r--r-- | gcc/config/riscv/riscv-vector-builtins-bases.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index abf03ba..5ee7d31 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -2548,6 +2548,7 @@ static CONSTEXPR const freducop<UNSPEC_ORDERED, HAS_FRM> vfredosum_frm_obj; static CONSTEXPR const reducop<SMAX> vfredmax_obj; static CONSTEXPR const reducop<SMIN> vfredmin_obj; static CONSTEXPR const widen_freducop<UNSPEC_UNORDERED> vfwredusum_obj; +static CONSTEXPR const widen_freducop<UNSPEC_UNORDERED, HAS_FRM> vfwredusum_frm_obj; static CONSTEXPR const widen_freducop<UNSPEC_ORDERED> vfwredosum_obj; static CONSTEXPR const widen_freducop<UNSPEC_ORDERED, HAS_FRM> vfwredosum_frm_obj; static CONSTEXPR const vmv vmv_x_obj; @@ -2810,6 +2811,7 @@ BASE (vfredmin) BASE (vfwredosum) BASE (vfwredosum_frm) BASE (vfwredusum) +BASE (vfwredusum_frm) BASE (vmv_x) BASE (vmv_s) BASE (vfmv_f) |